Processor architecture

• US 20050076187A1
• Filed: 10/19/2001
• Published: 04/07/2005
• Est. Priority Date: 12/19/2000
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Mindspeed Technologies UK Limited (MACOM Technology Solutions Holdings, Inc.)
• Inventors: Claydon, Anthony Peter John
• Granted Patent: US 8,386,752 B2
• Time in Patent Office: Days
• US Class Current: 712/11
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

There is described a processor architecture having a plurality of processing elements, each element having at least one input port and at least one output port, each port having at least a data bus and a valid data signal line; and a bus structure which contains a plurality of switches which are arranged so as to allow an output port of any first processing element to be connected to the input port of any second processing element for a time interval, in which each processing element is enabled to set a value on the valid data signal line of its output port to a first logic state when the associated data bus contains a transfer value, and to a second logic state when the data bus does not contain a transfer value, and in which each processing element is further enabled to enter a waiting state for a predetermined time interval when the value on the valid data signal line of the associated input port is in the second logic state. This reduces the power consumption of the device.

Claims

1. A processor architecture comprising:

a plurality of processing elements, each element having at least one input port and at least one output port, each port having at least a data bus and a valid data signal line; and

a bus structure which contains a plurality of switches which are arranged so as to allow an output port of any first processing element to be connected to the input port of any second processing element for a time interval;

each processing element being enabled to set a value on the valid data signal line of its output port to a first logic state when the associated data bus contains a transfer value, and to a second logic state when the data bus does not contain a transfer value;

each processing element being further enabled to enter a waiting state for a predetermined time interval when the value on the valid data signal line of the associated input port is in the second logic state.

2. A processor architecture as claimed in claim 1, wherein the processing element is programmable in such a way as to set the predetermined time interval.

3. A processor architecture as claimed in claim 1, wherein the processing element is enabled, after entering the waiting state for the predetermined time interval, to reexamine the value on the valid data signal line.

4. A processor architecture as claimed in claim 1, 2 or 3, wherein the processing element is further enabled to load data from the data bus of its input port when the value on the valid data signal line of the associated input port is in the first logic state.

5. A processor architecture as claimed in any preceding claim, wherein the bus structure and the input and output ports of each processing elements contain a first number of bits, and wherein the transfer value may contain any number of bits less than or equal to the first number.

6. A processor architecture as claimed in claim 5, wherein the second processing element is enabled to load any number of bits less than or equal to the first number of bits.

7. A processor architecture as claimed in any preceding claim, wherein the input port of each processing element is connected to the bus structure at a location in front of a location at which the corresponding output port is connected to the bus structure, in the direction of signal flow, such that, during a transfer time period, the second processing element may set a second transfer value on the bus structure.

8. A processor architecture as claimed in claim 7, wherein, in the absence of a second transfer value set on the bus structure, the processing element is enabled to set a predetermined value on the bus structure.

9. A processor architecture as claimed in any preceding claim, wherein the processing elements include memory elements, for storing received data.

10. A processor architecture as claimed in claim 9, wherein the processing elements include processing elements, for operating on received data, and memory elements, for storing received data.

11. A processor architecture as claimed in any preceding claim, wherein the processing elements include Arithmetic Logic Units.

12. A processor architecture as claimed in any preceding claim, wherein the processing elements include Multiplier Accumulators.

13. A processor architecture as claimed in any preceding claim, each processing element having:

a first input for receiving data from a first bus;

a first output for transferring data to the first bus;

a second input for receiving data from a second bus;

a second output for transferring data to the second bus.