Pin assignment in block-based integrated circuit design methodologies

• US 20050076319A1
• Filed: 10/03/2003
• Published: 04/07/2005
• Est. Priority Date: 10/03/2003
• Status: Abandoned Application

• Current Assignee: AmmoCore Technology, Inc.
• Original Assignee: AmmoCore Technology, Inc.
• Inventors: Chow, Shau-Lim Stan, Yue, Kwok Ming
• Application Number:
  US10/678,466
• Publication Number:
  US 20050076319A1
• Time in Patent Office: Days
• US Class Current: 716/122
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

In pin assignment for blocks in a netlist, each one of a plurality of pins are first assigned to a respective one of a plurality of first locations along a periphery a block in accordance with top-down criteria and components are then placed within in the block in relative proximity to the pins with which the components connect. Each of the pins may then be moved to a respective second location within the block proximal the components to which such pins connect in accordance with bottom-up criteria. The components may then have their placement refined in accordance to their relative position to the pins connecting to such components at the second location.

Claims

1. A method of pin assignment in a block in a block-based integrated circuit design process, the method comprising steps of:

assigning within the block a plurality of block pins to a respective one of a plurality of first locations;

placing in the block a plurality of components wherein each of the components is placed relatively proximal to the pins respectively connecting to each of the components;

moving selected ones of the pins to a respective one of second locations proximal the components connecting to the selected ones of the pins; and

refining placement of the components with respect to the selected ones of the pins at the second location connecting thereto.

2. A method as set forth in claim 1 wherein said assigning step includes the steps of:

locating the first locations proximal a periphery of the block; and

placing the pins in the first locations in accordance with connectivity constraints to other such pins connecting thereto contained in other such blocks at a current hierarchical level of the integrated circuit.

3. A method as set forth in claim 2 wherein said placing step is performed using a heuristic based on a shortest distance of each of the pins in the block to pins in other such blocks to which each of the pin connects.

4. A method as set forth in claim 2 wherein global routing to detect blockages and congestion is used to avoid the blockages and congestion while routing a connection from each of the pins to the pins in the other blocks.

5. A method as set forth in claim 2 wherein said placing step includes the step of selecting from a criticality ranking associated with each of the timing paths a most critical timing path between the block and one other of such blocks such that the pins on the most critical path are first assigned and pins on remaining timing paths assigned in order of decreasing criticality ranking.

6. A method as set forth in claim 2 wherein said placing step includes the step of maintaining parallel alignment of bus pins in the block to corresponding bus pins in one other of the blocks, wherein the bus pins in the block and the one other of the blocks are each abstracted as a single distributed pin.

7. A method as set forth in claim 1 wherein said moving step includes the steps of:

defining a bounding box containing a plurality of component pins of selected ones of the components to which a respective one of the block pins connects; and

distributing each respective one of the block pins into the bounding boxe containing the component pins to which it connects.

8. A method as set forth in claim 7 wherein said distributing step and said refining step are reiteratively performed.

9. A method as set forth in claim 1 wherein said moving step includes the step of abstracting a shape of each of the pins from a small shape to a distributed shape to enhance routability at a top hierarchical level of the integrated circuit.

10. A method as set forth in claim 1 wherein the block has a plurality of metal layers, the pins being in a selected one of the metal layers.

11. A method as set forth in claim 10 wherein the width of the pins is substantially equivalent to a minimum layer width of the selected one of the metal layers.

12. A method as set forth in claim 11 wherein the width of one of the pins is a width of a net to which the one of the pins is contained in the event the width of the net is required to be larger than the minimum layer width.

13. A method as set forth in claim 10 wherein a minimum spacing of the pins is substantially equivalent to a minimum layer spacing rule established for the selected one of the layers.

14. A method as set forth in claim 13 wherein the spacing between two selected ones of the pins is larger than the minimum layer spacing for the selected one of the layers in the event a net containing the two selected ones of the pins requires a larger spacing than the minimum spacing.

15. A method as set forth in claim 10 wherein one of a power net and ground net is interposed the pins of a first signal net and the pins of a second signal net in the event one of the power net and the ground net is interposed the first and second signal net.

16. A method as set forth in claim 1 further comprising the steps of:

defining a virtual pin to a selected location in a temporary top metal layer of the block;

routing between the virtual pin and a further pin in a lower metal layer within the block wherein at least one via is formed between the temporary top layer and a lower metal layer immediately below the temporary layer; and

abstracting the block wherein the top metal layer and the via are removed, one of the pins being assigned in the second metal layer to the selected location immediately below the removed via.

17. A method as set forth in claim 16 wherein the virtual pin is included in a blockage in the top layer, the blockage preventing routing of the temporary layer within the block.

18. A method of pin assignment in a plurality of blocks in a netlist, the method comprising steps of:

assigning within each of the blocks a plurality of block pins to a respective one of a plurality of first locations;

placing in each of the blocks a plurality of components wherein each of the components is placed relatively proximal to the pins respectively connecting to each of the components;

moving selected ones of the pins to a respective one of second locations proximal the components connecting to the selected ones of the pins; and

refining placement of the components with respect to the selected ones of the pins at the second location connecting thereto.

19. A method as set forth in claim 18 wherein said assigning step includes the steps of:

locating the first locations proximal a periphery of each of the blocks; and

placing the pins in the first locations in one of the blocks in accordance with connectivity constraints to the pins connecting thereto contained in other such blocks at a current hierarchical level of the netlist.

20. A method a set forth in claim 19 wherein said placing step is performed using a heuristic based on a shortest distance of each of the pins in one of the blocks to pins in other ones of the blocks to which each of the pin connects.

21. A method as set forth in claim 19 wherein global routing to detect blockages and congestion is used to avoid the blockages and congestion while routing a connection from each of the pins to the pins in the other ones of blocks.

22. A method as set forth in claim 19 wherein said placing step includes the step of selecting from a criticality ranking associated with each of the timing paths a most critical timing path between the block and one other of the blocks such that the pins on the most critical path are first assigned and pins on remaining timing paths assigned in order of decreasing criticality ranking.

23. A method as set forth in claim 19 wherein said placing step includes the step of maintaining parallel alignment of bus pins in one of the blocks to corresponding bus pins in one other of the blocks, wherein the bus pins in the one of the blocks and the one other of the blocks are each abstracted as a single distributed pin.

24. A method as set forth in claim 18 wherein said moving step includes the steps of:

defining a plurality of bounding boxes wherein each one of the bounding boxes contains a plurality of component pins of selected ones of the components to which a respective one of the block pins connects; and

distributing each respective one of the block pins into the one of the bounding boxes containing the component pins to which it connects.

25. A method as set forth in claim 24 wherein said distributing step and said refining step are reiteratively performed.

26. A method as set forth in claim 18 wherein said moving step includes the step of abstracting a shape of each of the pins from a small shape to a distributed shape to enhance routability at a top hierarchical level of the integrated circuit.

27. A method as set forth in claim 18 wherein each of the blocks has a plurality of metal layers, the pins being in a selected one of the metal layers.

28. A method as set forth in claim 27 wherein the width of the pins is substantially equivalent to minimum layer width of the selected one of the metal layers.

29. A method as set forth in claim 28 wherein the width of each one of the pins is a width of a net to which each one of the pins is contained in the event the width of the net is required to be larger than the minimum layer width.

30. A method as set forth in claim 27 wherein a minimum spacing of the pins is substantially equivalent to a minimum layer spacing established for the selected one of the layers.

31. A method as set forth in claim 30 wherein the spacing between two selected ones of the pins is larger than the minimum layer spacing for the selected one of the layers in the event a net containing the two selected ones of the pins requires a larger spacing than the minimum layer spacing.

32. A method as set forth in claim 27 wherein one of a power net and ground net is interposed the pins of a first signal net and the pins of a second signal net in the event one of the power net and the ground net is interposed the first and second signal net.

33. A method as set forth in claim 18 further comprising the steps of:

defining a virtual pin to a selected location in a temporary top metal layer of one of the blocks;

routing between the virtual pin and a further pin in a lower metal layer within the one of blocks wherein at least one via is formed between the temporary top layer and a lower metal layer immediately below the temporary layer; and

abstracting the one of blocks wherein the top metal layer and the via are removed, one of the pins being assigned in the second metal layer to the selected location immediately below the removed via.

34. A method as set forth in claim 33 wherein the virtual pin is included in a blockage in the top layer, the blockage preventing routing of the temporary layer within the block.

35. A method as set forth in claim 18 wherein the assigning, placing, moving and refining steps are performed on each of the blocks sequentially with respect to each other of the blocks at the current hierarchical level in the netlist.