Method of forming one-transistor memory cell and structure formed thereby
First Claim
1. A method of forming a one-transistor memory cell, comprising:
- (a) forming a dielectric layer over a substrate having a pass-gate formed thereon;
(b) forming an opening in the dielectric layer to expose a portion of the substrate at least adjacent to the pass-gate;
(c) forming a capacitor dielectric layer on sidewalls of the opening in the dielectric layer and on the exposed portion of the substrate; and
(d) forming an electrode layer over the capacitor dielectric layer.
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Accused Products
Abstract
A method of forming a one-transistor memory cell includes the steps of: forming a dielectric layer over a substrate having a pass-gate formed thereon; forming an opening in the dielectric layer to expose a portion of the substrate at least adjacent to the pass-gate; forming a capacitor dielectric layer on sidewalls of the opening in the dielectric layer and on the exposed portion of the substrate; and forming an electrode layer over the capacitor dielectric layer. A one-transistor memory cell is also disclosed. The one-transistor memory cell has a substrate having a pass-gate formed thereover. A dielectric layer is formed over the pass-gate and the substrate and has an opening exposing a portion of the substrate adjacent to the pass-gate. A capacitor dielectric layer is formed on sidewalls of the opening and on the exposed portion of the substrate. An electrode layer is formed on the capacitor dielectric layer.
30 Citations
52 Claims
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1. A method of forming a one-transistor memory cell, comprising:
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(a) forming a dielectric layer over a substrate having a pass-gate formed thereon;
(b) forming an opening in the dielectric layer to expose a portion of the substrate at least adjacent to the pass-gate;
(c) forming a capacitor dielectric layer on sidewalls of the opening in the dielectric layer and on the exposed portion of the substrate; and
(d) forming an electrode layer over the capacitor dielectric layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method of forming a one-transistor memory cell, comprising:
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(a) forming an isolation region within a substrate, a pass-gate over the substrate and a first dielectric layer over the substrate including over the isolation region and the pass-gate;
(b) forming an opening through the first dielectric layer to expose a portion of the substrate at least adjacent to the pass-gate, wherein a second dielectric layer on a sidewall of the pass-gate is used as an etch stop layer, and a recess within the isolation region;
(c) forming a capacitor dielectric layer on sidewalls of the opening in the first dielectric layer, at least partially within the recess of the isolation region and on the exposed portion of the substrate;
(d) forming an electrode layer over the capacitor dielectric layer;
(e) forming a source/drain (S/D) region within the substrate and adjacent to the pass-gate; and
(f) forming a doped region within the substrate and adjacent to the pass-gate and the electrode layer. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23)
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24-38. -38. (canceled)
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39. A method of forming a one-transistor memory cell, comprising:
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(a) forming a dielectric layer over a substrate having a pass gate formed thereon;
(b) forming an opening in the dielectric layer to expose at least a portion of the substrate adjacent to the pass-gate;
(c) conformally forming a capacitor dielectric layer on sidewalls of the opening in the dielectric layer and on the exposed portion of the substrate; and
(d) conformally forming an electrode layer over the capacitor dielectric layer along sidewalls of the opening in the dielectric layer and over the exposed portion of the substrate, leaving a remaining portion of said opening. - View Dependent Claims (40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52)
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Specification