Fully depleted silicon-on-insulator CMOS logic

• US 20050077564A1
• Filed: 09/27/2004
• Published: 04/14/2005
• Est. Priority Date: 10/09/2003
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard
• Granted Patent: US 7,078,770 B2
• Time in Patent Office: Days
• US Class Current: 257/314
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/78615 with a body contact
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7923 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A extractor implanted region is used in a silicon-on-insulator CMOS memory device. The extractor region is reversed biased to remove minority carriers from the body region of partially depleted memory cells. This causes the body region to be fully depleted without the adverse floating body effects.

Claims

1. A transistor having a silicon-on-insulator structure on a substrate, the transistor comprising:

a drain region comprising a first doped material and formed in the silicon-on-insulator;

a source region comprising the first doped material and formed in the silicon-on-insulator;

a control gate formed above and substantially between the drain and source regions; and

an extractor contact, in the silicon-on-insulator, comprising a second doped material and coupled to a depletion region substantially between the drain and source regions, the depletion region being fully depleted in response to a reverse bias of the extractor contact.

2. The transistor of claim 1 wherein the first doped material is comprised of n-type silicon and the second doped material is comprised of p-type silicon.

3. The transistor of claim 1 wherein the first doped material is comprised of p-type silicon and the second doped material is comprised of n-type silicon.

4. The transistor of claim 1 wherein the extractor contact is coupled to a p-type silicon on the insulator.

5. The transistor of claim 1 wherein the extractor contact is coupled to an n-type silicon on the insulator.

6. The cell of claim 5 wherein the reverse bias voltage is greater than a drain voltage applied to the drain region for cell operation.

7. The cell of claim 5 wherein the reverse bias voltage is less than a voltage applied to substrate for cell operation.

8. The cell of claim 7 wherein the substrate voltage is ground potential.

9. The cell of claim 5 wherein a positive voltage is applied to the gate in order to erase a charge stored in the cell.

10. The cell of claim 5 wherein the extractor contact is comprised of p-type silicon.

11. The cell of claim 5 wherein the high dielectric constant gate insulator comprises an oxide-nitride-oxide layer.

5-1. A vertical multiple bit memory cell having a silicon-on-insulator structure on a substrate, the memory cell comprising:

a vertical metal oxide semiconductor field effect transistor (MOSFET) extending horizontally outward from a substrate, the MOSFET having a drain region, a source region, a channel region between the source and drain regions, and a gate separated from the channel region by a high dielectric constant gate insulator that can store a first charge in a first storage region and a second charge in a second storage region;

a first transmission line coupled to the drain region;

a second transmission line coupled to the source region; and

an extractor contact coupled to the channel region in the silicon-on-insulator such that a reverse bias voltage on the extractor contact fully depletes the channel region.

12. An electronic system, comprising:

a processor; and

a memory device coupled to the processor, wherein the memory device includes a memory array having a plurality of memory cells with a silicon-on-insulator structure, each memory cell comprising;

a drain region comprising a first doped material and formed in the silicon-on-insulator,

a source region comprising the first doped material and formed in the silicon-on-insulator;

a control gate formed above and substantially between the drain and source regions; and

an extractor contact comprising a second doped material and coupled to a depletion region in the silicon-on-insulator substantially between the drain and source regions, the depletion region being fully depleted in response to a reverse bias of the extractor contact.

13. The electronic system of claim 12 wherein the memory cell is a vertical memory cell.

14. The electronic system of claim 12 and further including an oxide-nitride-oxide layer between the control gate and the silicon-on-insulator.

15. The electronic system of claim 12 wherein the memory device is a flash memory device.

16. The electronic system of claim 15 wherein the flash memory device is a NAND flash memory device.

17. A silicon-on-insulator inverter comprising:

a PMOS transistor formed in an n+ well in an insulator structure on a substrate, the transistor comprising;

a drain region comprising a first p+ doped region in the n+ well;

a source region comprising a second p+ doped region in the n+ well;

an control gate formed above and substantially between the drain and source regions; and

an extractor contact coupled to a depletion region in the n+ well substantially between the drain and source regions, the depletion region being fully depleted in response to a reverse bias of the extractor contact; and

an NMOS transistor coupled to the PMOS transistor and formed in a p+ well in the insulator structure on the substrate, the transistor comprising;

a drain region comprising a first n+ doped region in the p+ well, the drain region coupled to the NMOS source region;

a source region comprising a second n+ doped region in the p+ well;

a control gate formed above and substantially between the drain and source regions, the PMOS control gate coupled to the NMOS control gate; and

an extractor contact coupled to a depletion region in the p+ well substantially between the drain and source regions, the depletion region being fully depleted in response to a reverse bias of the extractor contact.

18. The inverter of claim 17 wherein a bias voltage of V_DD is coupled to the PMOS drain region and the PMOS extractor contact is biased at a voltage greater than V_DD and the NMOS extractor contact is biased at a voltage less than ground potential.

19. A The inverter of claim 17 wherein the NMOS source region is coupled to ground potential.

20. The inverter of claim 17 wherein the reverse bias on the PMOS extractor contact is a voltage greater than V_DD and the reverse bias on the NMOS extractor contact is a voltage less than ground potential.