Power control system startup method and circuit

• US 20050077933A1
• Filed: 10/14/2003
• Published: 04/14/2005
• Est. Priority Date: 10/14/2003
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Sukup, Frantisek, Hall, Jefferson W., Halamik, Josef
• Granted Patent: US 6,940,320 B2
• Time in Patent Office: Days
• US Class Current: 327/143
• CPC Class Codes: H02M 1/36 Means for starting or stopping converters

Abstract

A power control system uses two separate currents to control a startup operation of the power control system. One of the currents has a small value and is used to charge an output voltage to an initial value. Once the initial value is reached, a second current that has a large value is used to charge the output voltage to an operating voltage value.

Claims

1. A power control system startup method comprising:

coupling a high voltage device to receive an input voltage and responsively generate a bias current and couple the bias current to an output transistor of the high voltage device;

coupling a switch element to shunt the bias current away from the output transistor when an output voltage is less than a first value; and

coupling the output transistor of the high voltage device to generate an output current that is greater than the bias current when the output voltage is greater than the first value.

2. The method of claim 1 wherein coupling the high voltage element to receive the input voltage and responsively generate the bias current and couple the bias current to an output transistor of the high voltage element includes coupling a first current carrying electrode of a J-FET transistor to receive the input voltage, coupling second current carrying electrode of the J-FET transistor to a first current carrying electrode of the output transistor, coupling a resistor to receive a current from the second current carrying electrode of the J-FET transistor and couple the bias current to a control electrode of the output transistor.

3. The method of claim 2 wherein coupling the switch element to shunt the bias current away from the output transistor when the output voltage is less than the first value includes coupling a pinch resistor to shunt the bias current away from the output transistor.

4. The method of claim 3 wherein coupling the pinch resistor to shunt the bias current away from the output transistor includes coupling a first terminal of the pinch resistor to the control electrode of the output transistor and a second terminal to an output for forming the output voltage.

5. The method of claim 2 wherein coupling the switch element to shunt the bias current away from the output transistor when the output voltage is less than the first value includes coupling a comparator coupled MOS transistor to shunt the bias current away from the output transistor.

6. The method of claim 5 wherein coupling the comparator coupled MOS transistor to shunt the bias current away from the output transistor includes coupling a first current carrying electrode of the comparator coupled MOS transistor to the control electrode of the output transistor, coupling a second carrying electrode of the comparator coupled MOS transistor to an output, and coupling a control electrode of the comparator coupled MOS transistor to receive a reference voltage.

7. The method of claim 6 further including stacking two threshold adjusted MOS transistors to form the reference voltage.

8. A power control system startup method comprising:

receiving an input voltage;

generating a first current from the input voltage;

shunting the first current to an output of a startup circuit;

using the first current to form an output voltage at the output; and

using a second current to form the output voltage when the output voltage is greater than a first value wherein the second current is greater than the first current.

9. The method of claim 8 wherein using the second current to form the output voltage at the output includes coupling the bias current to an output transistor of the startup circuit when the output voltage is greater than the first value.

10. The method of claim 8 wherein shunting the first current to the output of the startup circuit includes enabling a pinch resistor to couple the first current to the output.

11. The method of claim 10 wherein enabling the pinch resistor to couple the first current to the output includes coupling the pinch resistor between the output and a control electrode of an output transistor of the startup circuit, and enabling the pinch resistor when the output voltage is less than a pinch-off voltage of the pinch resistor.

12. The method of claim 8 wherein shunting the first current to the output of the startup circuit includes enabling a comparator transistor to couple the first current to the output.

13. The method of claim 12 wherein enabling the comparator transistor to couple the first current to the output includes forming a reference voltage, applying the reference voltage to a control electrode of the comparator transistor, and coupling the comparator transistor between a control electrode of an output transistor and the output.

14. The method of claim 8 further including coupling the output to a voltage return to disable the power control system.

15. A power control system method comprising:

generating a first output current at an output of a startup circuit responsively to a first value of an output voltage; and

coupling the output to a voltage return to disable the output voltage.

16. The method of claim 15 wherein generating the first output current at the output of the startup circuit responsively to the first value of the output voltage includes coupling a bias current to the output and disabling an output transistor of the startup circuit.

17. The method of claim 16 wherein coupling the bias current to the output and disabling the output transistor of the startup circuit includes shunting the bias current from a control electrode of the output transistor to the output of the startup circuit.

18. The method of claim 17 wherein shunting the bias current from the control electrode of the output transistor to the output of the startup circuit includes enabling a pinch resistor to shunt the bias current.

19. The method of claim 16 wherein generating the first output current at the output of the startup circuit responsively to the first value of the output voltage includes enabling the output transistor to generate the first output current.

20. The method of claim 19 wherein enabling the output transistor to generate the first output current includes coupling a J-FET transistor to a high voltage input to generate a bias current, and coupling the bias current to the output transistor to enable the output transistor.