Tiled electronic display structure

• US 20050078104A1
• Filed: 10/01/2004
• Published: 04/14/2005
• Est. Priority Date: 02/17/1998
• Status: Active Grant

• Current Assignee: MEC Management, LLC (Three Affiliated Tribes of the Fort Berthold Reservation, North Dakota)
• Original Assignee: Transpacific Infinity LLC
• Inventors: Atherton, James Harold, Shen, Zilan, Matthies, Dennis Lee, Stewart, Roger Green, Busta, Heinz H., Bechis, Dennis J.
• Granted Patent: US 7,592,970 B2
• Time in Patent Office: Days
• US Class Current: 345/204
• CPC Class Codes: G02F 1/13336 Combining plural substrates to produce large-area displays, e.g. tiled displays
• CPC Class Codes: G02F 1/133512 Light shielding layers, e.g. black matrix G02F1/136209 takes precedence
• CPC Class Codes: G09G 2300/026 Video wall, i.e. juxtaposition of a plurality of screens to create a display screen of bigger dimensions
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2320/048 using evaluation of the usage time
• CPC Class Codes: G09G 3/3208 organic, e.g. using organic light-emitting diodes [OLED]
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 27/156 two-dimensional arrays
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H10K 50/85 Arrangements for extracting light from the devices
• CPC Class Codes: H10K 50/86 Arrangements for improving contrast, e.g. preventing reflection of ambient light
• CPC Class Codes: H10K 59/18 Tiled displays
• CPC Class Codes: H10K 59/875 Arrangements for extracting light from the devices
• CPC Class Codes: H10K 59/8791 Arrangements for improving contrast, e.g. preventing reflection of ambient light

Abstract

A tiled display device is formed from display tiles having picture element (pixel) positions defined up to the edge of the tiles. Each tile includes a memory which stores display data, and pixel driving circuitry which controls the scanning and illumination of the pixels on the tile. The tiles are formed in two parts, an electronics section and a display section. Each of these parts includes connecting pads which cover several pixel positions. Each connecting pad makes an electrical connection to only one row electrode or column electrode. The connecting pads on the display section are electrically connected and physically joined to corresponding connecting pads on the electronics section to form a complete tile.

Claims

1. An electronic display structure comprising:

a plurality of pixel structures, arranged in a matrix having rows and columns and including a plurality of contacts for receiving electrical signals;

a circuit board having a top surface and a bottom surface;

a memory coupled to the bottom surface of the circuit board, the memory storing image data to be displayed;

pixel driving circuitry coupled to the bottom surface of the circuit board and responsive to the image data stored in the memory to provide a plurality of electrical signals which are conditioned to activate respective ones of the plurality of pixel structures;

timing circuitry, coupled to the bottom surface of the circuit board and responsive to a timing signal to sequentially scan the pixel driving circuitry to provide electrical signals to successive rows of the matrix of pixel structures;

a plurality of electrical contacts coupled to the top surface of the circuit board to receive the plurality of electrical signals provided by the pixel driving circuitry, the plurality of electrical contacts having a one-to-one correspondence with the plurality of contacts of the matrix of pixel structures, and

means for coupling the plurality of electrical contacts on the top surface of the circuit board to the plurality of contacts of the matrix of pixel structures.

2. An electronic display structure according to claim 1, further comprising:

a further memory for storing image correction information, the image correction information indicating, for each pixel structure, a difference between an actual illumination level of the pixel structure and a respective desired illumination level for the pixel structure,

compensation circuitry, coupled to the further memory and to the pixel driving circuitry for adjusting each pixel structure in brightness as it is driven by the pixel driving circuitry to compensate for the difference between the actual illumination level of the pixel structure and the respective desired illumination level of the pixel structure.

3. An electronic display structure according to claim 2, wherein:

the pixel driving circuitry includes pulse-width modulation circuitry which achieves gray scale in a pixel structure by changing relative amounts of time that the pixel structure is illuminated and not illuminated; and

the compensation circuitry includes variable supply circuitry which adjusts operational power applied to each pixel structure to illuminate the pixel structure.

4. An electronic display structure according to claim 3, wherein each pixel structure includes a plurality of sub-pixel elements and the memory stores separate pixel data for each of the sub-pixel elements and the further memory stores separate correction information for each of the sub-pixel elements.

5. An electronic display structure according to claim 1, wherein the timing circuitry sequentially scans each row of the matrix of pixel structures and the pixel driving circuitry illuminates only the pixel elements in the row of the matrix which is currently scanned by the timing circuitry.

6. An electronic display structure according to claim 5, wherein:

each of the pixel structure includes an organic light emitting diode (OLED) display material;

and the compensation circuitry includes a plurality of variable current sources which are controlled by the image correction information in the further memory to adjust a respective amount of current applied to each pixel structure in a row of pixel structures as the row of pixel structures is selected by the timing circuitry.

7. A seamless tiled electronic display structure according to claim 1 wherein, each tile has a plurality of edges and for at least one tile of the plurality of tiles the pixel structures along the edges of the at least one tile are configured to mate with adjacent pixel structures on respective other ones of the plurality of tiles to form respective seamless junctions along each of the edges of the at least one tile.

8. A tiled display structure comprising a plurality of image tiles, each tile comprising

a plurality of pixel structures, arranged in a matrix having rows and columns and including a plurality of contacts for receiving electrical signals;

a circuit board having a top surface and a bottom surface;

a memory coupled to the bottom surface of the circuit board, the memory storing image data to be displayed;

pixel driving circuitry coupled to the bottom surface of the circuit board and responsive to the image data stored in the memory to provide a plurality of electrical signals which are conditioned to activate respective ones of the plurality of pixel structures;

timing circuitry, coupled to the bottom surface of the circuit board and responsive to a timing signal to sequentially scan the pixel driving circuitry to provide electrical signals to successive rows of the matrix of pixel structures;

a plurality of electrical contacts coupled to the top surface of the circuit board to receive the plurality of electrical signals provided by the pixel driving circuitry, the plurality of electrical contacts having a one-to-one correspondence with the plurality of contacts of the matrix of pixel structures, and

means for coupling the plurality of electrical contacts on the top surface of the circuit board to the plurality of contacts of the matrix of pixel structures; and

a rigid back panel structure including rigid connections which provide operational power to the plurality of image tiles, and which hold the plurality of image tiles in position to form the tiled display structure.

9. A tiled display structure according to claim 8, wherein the back panel structure includes further rigid connections which provide the image data and timing signals to the plurality of image tiles.

10. A tiled display structure according to claim 8, wherein each image tile includes an optical receiving module and the back panel structure includes further rigid connections which provide optical signals conveying image data and timing signals to each of the plurality of image tiles.

11. A tiled display structure according to claim 8, wherein each image tile includes an optical receiving module and the back panel structure includes an optical transmitter which broadcasts timing information to all image tiles concurrently.

12. A tiled display structure comprising a plurality of image tiles, each tile comprising

a plurality of pixel structures, arranged in a matrix having rows and columns and including a plurality of contacts for receiving electrical signals;

a circuit board having a top surface and a bottom surface;

a memory coupled to the bottom surface of the circuit board, the memory storing image data to be displayed;

pixel driving circuitry coupled to the bottom surface of the circuit board and responsive to the image data stored in the memory to provide a plurality of electrical signals which are conditioned to activate respective ones of the plurality of pixel structures;

timing circuitry, coupled to the bottom surface of the circuit board and responsive to a timing signal to sequentially scan the pixel driving circuitry to provide electrical signals to successive rows of the matrix of pixel structures;

a plurality of electrical contacts coupled to the top surface of the circuit board to receive the plurality of electrical signals provided by the pixel driving circuitry, the plurality of electrical contacts having a one-to-one correspondence with the plurality of contacts of the matrix of pixel structures, and

means for coupling the plurality of electrical contacts on the top surface of the circuit board to the plurality of contacts of the matrix of pixel structures; and

a back panel including a plurality of connectors, each of the connectors providing operational power to a respectively different one of the image tiles.

13. A tiled display structure according to claim 12, wherein the plurality of connectors are rigidly mounted on the back panel to define a matrix structure for mounting the tiles to form the tiled display structure.

14. A tiled display structure according to claim 13, wherein each image tile includes an optical receiving module and the back panel structure includes means for providing optical signals conveying image data and timing signals to each of the plurality of image tiles.

15. A tiled display structure according to claim 12, wherein each image tile includes an optical receiving module and the back panel structure includes further flexible connectors which provide optical signals conveying image data and timing signals to each of the plurality of image tiles.

16. A tiled display structure according to claim 12, wherein each image tile includes an optical receiving module and the back panel structure includes an optical transmitter which broadcasts timing information to all image tiles concurrently.