System and method for data synchronization for a computer architecture for broadband networks

• US 20050078117A1
• Filed: 10/18/2004
• Published: 04/14/2005
• Est. Priority Date: 03/22/2001
• Status: Active Grant

• Current Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Original Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Inventors: Yamazaki, Takeshi, Suzuoki, Masakazu
• Granted Patent: US 7,999,813 B2
• Time in Patent Office: Days
• US Class Current: 345/502
• CPC Class Codes: G06F 12/1466 Key-lock mechanism
• CPC Class Codes: H04L 69/12 Protocol engines

Abstract

A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A processing system for performing graphics processing is also provided. A first processor is of a first processor type and a number of second processors are of a second processor type. One of the second processors can perform graphics processing on a first set of graphics data to generate a second set of graphics data, and another of the second processors can perform graphics processing on the second set to generate a third set of graphics data.

Claims

1. A processing system for performing graphics processing, comprising:

a first processor of a first processor type; and

a plurality of second processors of a second processor type operatively connected to the first processor, at least a first selected one of the second processors being operable to perform a first graphics process on a first set of graphics data associated with a multi-dimensional object to generate a second set of graphics data, and a second selected one of the second processors being operable to perform a second graphics process on the second set of graphics data to generate a third set of graphics data.