Sub-micron high input voltage tolerant input output (I/O) circuit

• US 20050078421A1
• Filed: 12/03/2004
• Published: 04/14/2005
• Est. Priority Date: 01/09/2001
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Ajit, Janardhanan S.
• Granted Patent: US 6,985,015 B2
• Time in Patent Office: Days
• US Class Current: 361/56
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits
• CPC Class Codes: H03K 19/01818 for integrated injection logic (I2L)
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can handle. By placing input and output devices, in series, external voltages can be divided between the devices thereby reducing junction voltages seen by internal devices. By using external voltages as part of a biasing scheme for integrated circuit devices, stress created by the differential between external voltages and internal voltages can be minimized. Additionally device wells can be biased so that they are at a potential that is dependant on the external voltages seen by the low voltage integrated circuit.

Claims

1. An apparatus for generating a bias voltage at a bias node, the apparatus comprising:

a first input for accepting a pad voltage from an input/output circuit;

a second input for accepting an output enable signal;

a third input for accepting a first input voltage; and

an output circuit for providing the first input voltage to the bias node if the output enable signal is at an enable value and for providing a voltage proportional to the pad voltage to the bias node if the output enable signal is at a disable value.

2. The apparatus of claim 1, further comprising:

a fourth input for accepting a second input voltage, wherein the output circuit provides the first input voltage until the pad voltage is equal to the first input voltage if the output enable signal is at the disable value, wherein the output circuit provides an increasing voltage if the pad voltage is not less than the first input voltage but is less than the second input voltage minus an offset voltage, and wherein the output circuit provides a constant voltage if the pad voltage is greater than the second input voltage minus the offset voltage.

3. The apparatus of claim 2, wherein the offset voltage is equal to a threshold voltage of an N-channel Metal Oxide Semiconductor (NMOS).

4. The apparatus of claim 1, further comprising:

a fourth input for accepting a second input voltage; and

a threshold transistor coupled to the bias node at an output of the threshold transistor, wherein the bias voltage at the bias node is between the first input voltage plus a threshold voltage of the threshold transistor and the second input voltage minus the offset voltage of the threshold transistor.

5. The apparatus of claim 4, wherein the threshold transistor comprises a P-channel Metal Oxide Semiconductor (PMOS).

6. The apparatus of claim 1, further comprising:

a fourth input for accepting a second input voltage, wherein the bias voltage at the bias node is between the first input voltage plus a first offset voltage and the second input voltage minus a second offset voltage.

7. The apparatus of claim 6, wherein the first offset voltage is equal to a threshold voltage of an N-channel Metal Oxide Semiconductor (NMOS) and wherein the second offset voltage is equal to a threshold voltage of a P-channel Metal Oxide Semiconductor (PMOS).

8. The apparatus of claim 6, wherein the first offset voltage is equal to a threshold voltage of a P-channel Metal Oxide Semiconductor (PMOS) and wherein the second offset voltage is equal to a threshold voltage of an N-channel Metal Oxide Semiconductor (NMOS).

9. The apparatus of claim 6, wherein each of the first offset voltage and the second offset voltage is equal to a threshold voltage of a P-channel Metal Oxide Semiconductor (PMOS).

10. The apparatus of claim 6, wherein the second input voltage is about 3.3 Volts.

11. The apparatus of claim 10, wherein the first input voltage is between about 3.3 Volts and 1.2 Volts.

12. An apparatus for generating a first bias voltage, the apparatus comprising:

a first input for accepting a pad voltage;

an second input for accepting a second bias voltage, the second input having a corresponding output, the second bias voltage having a first voltage level if the corresponding output is enabled and having a second voltage level if the corresponding output is disabled; and

a circuit for providing the first voltage level of the second bias voltage as the first bias voltage if the pad voltage is less the second voltage level of the second bias voltage and for providing the pad voltage as the first bias voltage otherwise,

wherein the second voltage level of the second bias voltage is greater than the first voltage level of the second bias voltage.

13. The apparatus of claim 12, wherein the second voltage level is about 3.3 Volts and the first voltage level is about 1.2 Volts.

14. The apparatus of claim 12, further comprising a P-channel Metal Oxide Semiconductor (PMOS) for providing the second input and the corresponding output and an N-channel Metal Oxide Semiconductor (NMOS) for providing the first input.

15. A method for generating a bias voltage at a bias node using a bias circuit, the method comprising:

accepting a pad voltage from an input/output circuit node;

accepting a power supply voltage;

accepting an intermediate voltage;

providing a voltage derived from the power supply voltage or the intermediate voltage to the bias node if the power supply voltage is greater than a first predetermined value or the intermediate voltage is greater than a second predetermined value; and

providing a voltage derived from the pad voltage to the bias node if the power supply voltage is not greater than the first predetermined value and the intermediate voltage is not greater than the second predetermined value.

16. The method of claim 15, further comprising providing a voltage derived from the power supply voltage and the intermediate voltage to the bias node if the power supply voltage is greater than the first predetermined value and the intermediate voltage is greater than the second predetermined value.

17. A method for generating a bias voltage at a bias node using a bias circuit, the method comprising accepting a pad voltage from an input/output circuit node;

accepting a first input voltage;

accepting a second input voltage;

providing a first output voltage in a range between the second input voltage plus a first offset voltage and the first input voltage minus a second offset voltage to the bias node if the first input voltage is greater than a predetermined value; and

providing the bias voltage proportional to the pad voltage to the bias node if the first input voltage is not greater than a predetermined value.

18. The method of claim 17, wherein the first input voltage is a power supply voltage and the second input voltage is an intermediate voltage.

19. A method for generating a bias voltage at a bias node using a bias circuit, the method comprising:

accepting a pad voltage from an input/output circuit node;

accepting a power supply voltage;

providing a voltage derived from the power supply voltage to bias node if the power supply voltage is greater than a predetermined value; and

providing a voltage derived from the pad voltage to the bias node if the power supply voltage is not greater than the predetermined value.

20. The method of claim 19, wherein the predetermined value is about 3.3 Volts.