Hash and route hardware with parallel routing scheme
First Claim
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1. A multiprocessor switching chip, comprising:
- a receiver port;
a plurality of destination modules; and
a routing circuit coupled to receive a plurality of packets from the receiver port and programmably configured, for each received packet, to select a destination module for said received packet by calculating a routing signal using one or both of programmably selected control and data information extracted from the received packet as said received packet is being received, said routing circuit comprising a first table containing a plurality of independent rules that process data from the received packet in parallel as each packet is received to generate a rule table output for each rule contained in the first table; and
a second table containing a plurality of paths that combine the rule table outputs from the first table to generate a routing signal for the received packet.
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Abstract
A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a parallel routing scheme for calculating routing information for incoming packets. Using the programmable hash and route routing scheme, a hash and route circuit can be programmed for a variety of applications, such as routing, flow-splitting or load balancing.
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Citations
20 Claims
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1. A multiprocessor switching chip, comprising:
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a receiver port;
a plurality of destination modules; and
a routing circuit coupled to receive a plurality of packets from the receiver port and programmably configured, for each received packet, to select a destination module for said received packet by calculating a routing signal using one or both of programmably selected control and data information extracted from the received packet as said received packet is being received, said routing circuit comprising a first table containing a plurality of independent rules that process data from the received packet in parallel as each packet is received to generate a rule table output for each rule contained in the first table; and
a second table containing a plurality of paths that combine the rule table outputs from the first table to generate a routing signal for the received packet. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method for routing a packet to one of a plurality of destinations in a processor circuit, comprising:
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receiving at least a first packet on a receiver port of the processor circuit;
decoding said first packet to extract packet data and packet control information;
calculating a routing decision for the packet data based upon programmably selected information from the packet data or packet control information while the first packet is being received;
generating a routing result based upon the routing decision; and
transferring the first packet to a destination in the processor circuit identified by the routing result. - View Dependent Claims (15, 16, 17, 18, 19)
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20. A hash and route circuit for routing packet data extracted from a packet received on an input virtual channel to an output virtual channel, comprising:
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a decoder for decoding a received packet to extract packet data and input virtual channel information for the packet;
a rule table comprising a plurality of programmable rules, where each rule selects at least one byte from the packet data or the input virtual channel information and compares the selected at least one byte to an operand of the rule to generate a true/false result for the rule;
a path table coupled to receive the true/false results from the rule table, said path table comprising a plurality of entries which search for selected true/false results from the rule table and output path data from a matching entry; and
a routing table, wherein the path data from the path table may be directly output as an output virtual channel or may be used as an index to the route table which outputs an output virtual channel or may be used to select an output of a hash function as an index to the route table.
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Specification