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Hash and route hardware with parallel routing scheme

  • US 20050078601A1
  • Filed: 10/14/2003
  • Published: 04/14/2005
  • Est. Priority Date: 10/14/2003
  • Status: Active Grant
First Claim
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1. A multiprocessor switching chip, comprising:

  • a receiver port;

    a plurality of destination modules; and

    a routing circuit coupled to receive a plurality of packets from the receiver port and programmably configured, for each received packet, to select a destination module for said received packet by calculating a routing signal using one or both of programmably selected control and data information extracted from the received packet as said received packet is being received, said routing circuit comprising a first table containing a plurality of independent rules that process data from the received packet in parallel as each packet is received to generate a rule table output for each rule contained in the first table; and

    a second table containing a plurality of paths that combine the rule table outputs from the first table to generate a routing signal for the received packet.

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