Exponential channelized timer
First Claim
1. In an integrated circuit multichannel packet transfer device, a multichannel interval timer for generating a time-out pulse for each of a plurality of transfer channels, comprising:
- a counter comprising a first plurality of bits configured to increment through a multi-bit count in a free running loop;
for each of the plurality of transfer channels, a selection circuit for selecting from a plurality of input signals to generate a selected output signal in response to a control signal, where each of the plurality of input signals is coupled to a respective one of the first plurality of bits of the counter;
a control signal generator coupled to each selection circuit for generating a control signal for each transfer channel; and
a pulse generator coupled to the selected output signal from each selection circuit to generate a time-out pulse for each transfer channel whenever a transition in the selected output signal is detected, wherein the time-out pulse timing for each transfer channel is determined by the control signal.
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Accused Products
Abstract
A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a channelized timer for use in controlling the issuance of signals to the processor(s) or control logic (such as interrupts, descriptors, etc.) that that identify system-related functions for a plurality of channels. Using control registers to select an individual bit of a multi-bit counter, a timing interval pulse is provided for prompting signal generation that is otherwise subject to a minimum count requirement.
33 Citations
20 Claims
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1. In an integrated circuit multichannel packet transfer device, a multichannel interval timer for generating a time-out pulse for each of a plurality of transfer channels, comprising:
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a counter comprising a first plurality of bits configured to increment through a multi-bit count in a free running loop;
for each of the plurality of transfer channels, a selection circuit for selecting from a plurality of input signals to generate a selected output signal in response to a control signal, where each of the plurality of input signals is coupled to a respective one of the first plurality of bits of the counter;
a control signal generator coupled to each selection circuit for generating a control signal for each transfer channel; and
a pulse generator coupled to the selected output signal from each selection circuit to generate a time-out pulse for each transfer channel whenever a transition in the selected output signal is detected, wherein the time-out pulse timing for each transfer channel is determined by the control signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An apparatus comprising:
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a first interface circuit for receiving and transmitting packet data on a first channel;
a second interface circuit for receiving and transmitting packet data on a second channel;
a memory;
a packet manager circuit coupled to receive data on the first channel from the first interface circuit and to receive data on the second channel from the second interface circuit, wherein the packet manager circuit is configured to transmit data on the first and second channels to the memory under control of at least a first descriptor and a second descriptor, respectively, said packet manager being further configured to write back said at least a first descriptor to memory under control of a first time-out signal and to write back said at least a second descriptor to memory under control of a second time-out signal; and
a timer for generating the first and second time-out signals, comprising a multi-bit counter, a first and second multiplexer, each multiplexer having a select line, an output and multiple inputs, with each input coupled to a corresponding bit of the multi-bit counter, a first and second timer control register coupled respectively to the select lines of the first and second multiplexers, and a first and second pulse generator coupled to each multiplexer output for generating first and second time-out signals, wherein the first multiplexer selects one of the bits in the multi-bit counter for output to the first pulse generator in response to the first timer control register to generate the first time-out signal, and the second multiplexer selects one of the bits in the multi-bit counter for output to the second pulse generator in response to the second timer control register to generate the second time-out signal. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A method for generating time-out signals for a plurality of channels, comprising:
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running a free-running timer in a loop;
generating a first pulse whenever a transition is observed in a first selected bit position of the free-running timer, where said first pulse comprises a first time-out signal. - View Dependent Claims (18, 19, 20)
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Specification