Descriptor write back delay mechanism to improve performance

• US 20050078696A1
• Filed: 10/14/2003
• Published: 04/14/2005
• Est. Priority Date: 10/14/2003
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Oner, Koray
• Granted Patent: US 7,440,469 B2
• Time in Patent Office: Days
• US Class Current: 370/419
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence

Abstract

A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a descriptor write back timer mechanism for use in efficiently writing descriptors back to memory after transmitting data under control of the descriptors to inform the processor(s) about system-related functions for a plurality of channels. A timing interval pulse is provided for prompting descriptor write back operations that are otherwise subject to a minimum descriptor count requirement.

Claims

1. In an integrated circuit multichannel packet transfer device, an apparatus for transferring a plurality of data packets, comprising:

a first interface circuit for receiving packet data on a first channel;

a memory;

a packet manager circuit coupled between the first interface circuit and the memory to receive data on the first channel from the first interface circuit, wherein the packet manager circuit is configured to write at least a first data packet fragment to the memory under control of a first descriptor, and is configured to write at least a second data packet fragment to the memory under control of a second descriptor;

a timer for generating a first time-out signal at a predetermined time after the first descriptor is ready for transfer; and

a controller for controlling descriptor write back operations to memory in either read-modify-write mode or write-invalidate mode, wherein the controller writes a plurality of descriptors together to memory in a single write-invalidate operation if the plurality of descriptors is ready for transfer before the first time-out signal is generated.

2. The apparatus recited in claim 1, wherein the controller writes the plurality of descriptors separately to memory as a sequence of read-modify-write operations if the plurality of descriptors is not ready for transfer before the first time-out signal is generated.

3. The apparatus recited in claim 1, wherein the timer comprises

a multi-bit counter,

a multiplexer having one select line, one output and multiple inputs, with each input coupled to a corresponding bit of the multi-bit counter,

a timer control register coupled to the select line of the multiplexer, and

a first pulse generator coupled to the multiplexer output for generating the first time-out signals,

wherein the multiplexer selects one of the bits in the multi-bit counter for output to the pulse generator in response to the timer control register to generate the first time-out signal.

4. The apparatus recited in claim 1, where the memory comprises a cache memory having a line width of 2N, and the first and second descriptors each have a width of N.

5. The apparatus recited in claim 1, where the memory comprises a system memory and a cache memory, such that the packet manager writes data packets or descriptors to the system memory or cache memory.

6. The apparatus recited in claim 1, further comprising a register for storing a minimum descriptor count, whereby the controller writes a plurality of descriptors together to memory in a single write-invalidate operation only if the plurality of descriptors that are ready for transfer meets or exceeds the minimum descriptor count.

7. The apparatus recited in claim 1, where the timer comprises a memory device for programmably storing a timer setting to selectively determine the predetermined time at which the first time-out signal is generated.

8. The apparatus recited in claim 1, comprising:

a second interface circuit for transmitting packet data on a second channel;

an packet manager output circuit coupled between the memory and the second interface circuit to transmit data from the memory on the second channel, wherein the packet manager output circuit is configured to write output data packets to the second interface circuit under control of a plurality of output descriptors;

a timer for generating a second time-out signal a predetermined time after a first output descriptor is ready for transfer; and

a output controller for controlling output descriptor write back operations to memory in either read-modify-write mode or write-invalidate mode, wherein the output controller writes a plurality of output descriptors together to memory in a single write-invalidate operation if the plurality of output descriptors is ready for transfer before the second time-out signal is generated.

9. The apparatus recited in claim 8, wherein the output controller writes the plurality of output descriptors separately to memory as a sequence of read-modify-write operations if the plurality of output descriptors is not ready for transfer before the second time-out signal is generated.

10. A data transfer controller for managing the direct memory transfer of data on a first channel by releasing one or more descriptors associated with said first channel, where said data transfer controller is coupled to receive a time-out pulse for the first channel and is configured to delay release of said one or more descriptors until after receiving the time-out pulse for the first channel.

11. The data transfer controller recited in claim 10, wherein a plurality of descriptors received before the time-output pulse is generated are released together with a write-invalidate command.

12. The data transfer controller recited in claim 10, wherein a plurality of descriptors are released sequentially with read-modify-write commands when only one of the plurality of descriptors is received before the time-output pulse is generated.

13. The data transfer controller recited in claim 10, comprising a timer for generating a time-out pulse at a predetermined time interval after a first of the plurality of descriptors is received.

14. The data transfer controller recited in claim 13, wherein the predetermined time interval may be programmably selected from a plurality of timer interval values.

15. The data transfer controller recited in claim 10, comprising a packet manager input circuit for transferring a plurality of packets to memory under control of said one or more descriptors.

16. The data transfer controller recited in claim 10, comprising a packet manager output circuit for transferring a plurality of packets from memory under control of said one or more descriptors.

17. A method comprising:

receiving a first packet fragment in an interface circuit;

receiving a second packet fragment in the interface circuit;

transmitting the first and second packet fragments from the interface circuit to a memory under control of the first and second descriptors, respectively;

setting a timer to expire a predetermined time interval after the first descriptor for the first packet fragment is released; and

writing the first and second descriptors back to memory together as a write-invalidate command if the second descriptor is released before expiration of the timer.

18. The method recited in claim 17, further comprising writing the first and second descriptors back to memory separately as a sequence of read-modify-write commands if the second descriptor is not released before expiration of the timer.

19. The method recited in claim 17, wherein the first and second descriptors are written back to a cache memory having a line width of 2N, and the first and second descriptors each have a width of N.

20. The method of claim 19, wherein the first and second descriptors are written back to a cache memory having a line width of 32 B, and the first and second descriptors each have a width of 16 B.