SIGNAL PROCESSING DEVICE CAPABLE OF ENHANCING CORRECTNESS OF FEEDBACK SIGNALS

• US 20050078746A1
• Filed: 05/07/2004
• Published: 04/14/2005
• Est. Priority Date: 10/14/2003
• Status: Active Grant

• Current Assignee: Realtek Semiconductor Corp.
• Original Assignee: Realtek Semiconductor Corp.
• Inventors: Yen, Kuang-Yu, Kuo, Shieh-Hsing, Lin, Hou-Wei, Li, Yi-Lin
• Granted Patent: US 7,460,593 B2
• Time in Patent Office: Days
• US Class Current: 375/233
• CPC Class Codes: H04L 2025/0349 as a feedback filter
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/061 providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset removal of dc offset in coupling arrangements H04L25/029, H04L25/0296

Abstract

A signal processing device for processing a passband signal to generate an equalized signal includes a passband adaptive equalizer for generating the equalized signal according to the passband signal, including at least one feed-forward equalizer (FFE) and one feedback equalizer (FBE), and a multilevel quantizer coupled with the passband adaptive equalizer for selectively utilizing a single predetermined threshold or a plurality of multiple predetermined thresholds to quantize the equalized signal in order to generate a sliced signal.

Claims

1. A signal processing device for processing a passband signal to generate an equalized signal comprising:

a passband adaptive equalizer for generating the equalized signal according to the passband signal, comprising a feed-forward equalizer (FFE) and a feedback equalizer (FBE); and

a multilevel quantizer coupled with the passband adaptive equalizer for selectively utilizing a single predetermined threshold or a plurality of multiple predetermined thresholds to quantize the equalized signal in order to generate a sliced signal.

2. The device of claim 1 wherein the passband adaptive equalizer comprises an adder coupled respectively with the FFE and the FBE for outputting the equalized signal according to signals outputted from the FFE and the FBE.

3. The device of claim 1 further comprising:

a derotator coupled between the passband adaptive equalizer and the multilevel quantizer for derotating the equalized signal and inputting the derotated equalized signal into the multilevel quantizer; and

a rotator coupled between the multilevel quantizer and the passband adaptive equalizer for rotating the sliced signal outputted from the multilevel quantizer and inputting the rotated sliced signal into the passband adaptive equalizer.

4. The device of claim 3 wherein the rotator is coupled with the FBE for rotating the equalized signal, and the rotated sliced signal is a passband signal.

5. The device of claim 1 further comprising a control logic for controlling the multilevel quantizer to quantize the equalized signal by the single predetermined threshold or the plurality of multiple predetermined thresholds.

6. The device of claim 5 wherein the control logic controls the multilevel quantizer according to an error decision, the error decision comprises:

comparing the equalized signal with a predetermined level for a difference;

controlling the multilevel quantizer to quantize the equalized signal by the single predetermined threshold in the case that the difference is less than a predetermined threshold; and

controlling the multilevel quantizer to quantize the equalized signal by the plurality of multiple predetermined thresholds in the case that the difference is larger than a predetermined threshold.

7. The device of claim 5 wherein the control logic controls the multilevel quantizer according to stop-and-go decision, the stop-and-go decision comprises:

comparing the equalized signal with a predetermined level corresponding to the value of the sliced signal for a first difference;

comparing the equalized signal with a predetermined constant for a second difference;

controlling the multilevel quantizer to quantize the equalized signal by the single predetermined threshold for the sliced signal, in the case of the first difference and the second difference having the same sign (positive/negative); and

controlling the multilevel quantizer to quantize the equalized signal by the plurality of multiple predetermined thresholds for the sliced signal, in the case of the first difference and the second difference having different signs (positive/negative).

8. The device of claim 7 wherein the predetermined constant is determined by a constant modulus algorithm.

9. The device of claim 5 wherein the control logic controls the multilevel quantizer according to a mixture method, the method comprises:

comparing the equalized signal with a predetermined level corresponding to the value of the sliced signal for a first difference;

comparing the equalized signal with a predetermined constant for a second difference; and

controlling the multilevel quantizer to quantize the equalized signal by the single predetermined threshold for the sliced signal, in the case of the first difference being less than a predetermined threshold, or/and the first difference and the second difference have the same sign (positive/negative);

otherwise, controlling the multi-level quantizer to quantize the equalized signal by the plurality of multiple predetermined thresholds for the sliced signal.

10. The device of claim 9 wherein the predetermined constant is determined by a constant modulus algorithm.

11. The device of claim 1 wherein the sliced signal output by the multilevel quantizer has a plurality of bits.