Electronic control unit

• US 20050080529A1
• Filed: 05/17/2004
• Published: 04/14/2005
• Est. Priority Date: 09/26/2003
• Status: Active Grant

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Ishii, Akihiro, Hashimoto, Kohji, Iwagami, Yuki, Nakamoto, Katsuya
• Granted Patent: US 7,346,002 B2
• Time in Patent Office: Days
• US Class Current: 701/36
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: G06F 11/221 to test buses, lines or interfaces, e.g. stuck-at or open line faults

Abstract

A first control circuit section (master station) and a second control circuit section (substation) communicate with each other via series-parallel converters. The master station includes regular transmission device and transmission-permitting signal generation device; and the sub station includes regular report device, confirmation reply device relative to a transmission data from the master station, and an unprocessed data table. The unprocessed data table prevents jam-up in upstream communication from the sub station to the master station, enabling to carry out timely regular transmission and regular reporting. Transmission from the sub station to the master station is performed based on a transmission-permitting control signal that the master station generates. Consequently, it is possible to execute communication error processing and diminish communication control burden on the master station while properly performing the regular transmission and regular report between the master station and sub station.

Claims

1. An electronic control unit comprising:

a first control circuit section provided with a program memory including input/output control means and communication control means, an operation processing RAM memory, a microprocessor cooperating with said program memory, and a first series-parallel converter; and

a second control circuit section provided with a communication control circuit section for performing communication of a monitoring and control signal, a data memory, and a second series-parallel converter;

said first control circuit section and said second control circuit section mutually carrying out serial communication of monitoring signal and control signal via said first and second- series-parallel converters;

wherein said first control circuit section comprises regular transmission means and transmission-permitting control signal generation means, and said second control circuit section comprises confirmation reply means, regular report means, and an unprocessed data table;

said regular transmission means is means for regularly transmitting a control output data or a constant set data from said first control circuit section to said second control circuit section, and for writing and storing an output and set data having been normally received at said second control circuit section in said data memory;

said confirmation reply means is means for executing a confirmation reply of whether said second control circuit section has normally received or failed to receive data to be transmitted from said regular transmission means, and for requesting a retransmission processing from the first control circuit section to the second control circuit section in case of the receiving failure;

said regular report means is means for regularly reporting a monitoring input data and status information from said second control circuit section to said first control circuit section, and for storing the regular report data that said first control circuit section has normally received in said operation processing RAM memory;

said unprocessed data table acts as a receiving-side command memory of a first-in first-out structure that is provided in said second control circuit section, and arranged so as to sequentially save a command data for executing said regular report and a command data for executing a confirmation reply, and to sequentially erase said saved command data when transmitting a regular report and confirmation reply data to said first control circuit section; and

said transmission-permitting control signal generation means is control signal transmission means from said first control circuit section to said second control circuit section, by which the second control circuit section having received said signal starts to execute the transmission of the most first-in leading command in said unprocessed data table, and adds the latest monitoring input data and status information thereto and transmits a resulting command in the case where said leading command is a regular report.

2. The electronic control unit according to claim 1, wherein said transmission-permitting control signal generation means generates a control signal, a logic level of which inverts alternately every time said first control circuit section receives a regular report or a confirmation reply data from said second control circuit section.

3. The electronic control unit according to claim 1, wherein said first control circuit section further comprises regular report permission means;

and

said regular report permission means is means for storing a command data that is transmitted by said regular transmission means to a predetermined address of memory provided in said second control circuit section, and acts to permit said second control circuit section to transmit said regular report; and

a normal confirmation reply responsive to said regular transmission is replaced with the transmission of a regular report when the regular report is permitted.

4. The electronic control unit according to claim 1, wherein said first control circuit section further comprises irregular transmission means;

said second control circuit section further comprises report reply means;

said irregular transmission means acts as readout request means that is capable of being applied when there is any error in a report communication provided by said regular report means, and that is applied when necessary so that said first control circuit section may read out and confirm a monitoring input data of a specified address with respect to the second control circuit section, and may read out and check a write save data having been written and set by said regular transmission means;

said report reply means acts as communication means which performs a report reply of a monitoring input data or a write save data of a specified address as a confirmation reply to the fact that said second control circuit section has received said irregular transmission data, and to which a readout request is made again by retransmission request means provided in the first control circuit section on the supposition of presence of any communication error in said report reply; and

a communication command to said report reply means is stored once in said unprocessed data table, and transmitted to said first control circuit section along with a report reply data in response to a control signal provided by said transmission-permitting control signal generation means.

5. The electronic control unit according to claim 4, wherein said first control circuit section further comprises a reply-waiting data table and retransmission means;

said reply-waiting data table acts as a transmission-side command memory arranged so as to sequentially save a transmission command that said first control circuit section has transmitted by regular transmission means and irregular transmission means to the second control circuit section; and

to sequentially erase said save command when receiving a confirmation reply data or a report reply data from the second control circuit section; and

said retransmission means acts as means that operates when any communication error is present in a confirmation reply or a report reply to said regular transmission means or irregular transmission means or when a leading transmission command having been stored in said transmission-side command memory is not erased even if a predetermined time period has passed, and transmits again a transmission data based on said abnormal transmission command; and

a transmission command having been transmitted again is deleted from and stored again in said transmission-side command memory, thus a first-in first-out processing being carried out.

6. The electronic control unit according to claim 4, wherein said second control circuit section further comprises readout request setting means;

said readout request setting means acts as means for requesting readout of a selected data memory of a specified address, which is provided in said second control circuit section, by adding a readout request flag to status information contained in said regular report means; and

said first control circuit section is arranged to operate when any communication error is present in said regular report data or when said readout request is present, and to be capable of making a readout request for a regular report content or a selected data memory by said irregular transmission means.

7. The electronic control unit according to claim 4, wherein said first and second control circuit sections further comprise first and second communication error determination means, first and second adder-subtracters and first and second error occurrence definition means respectively;

said first and second communication error determination means act as receiving error determination means for determining the presence or absence of error as to various regular and irregular communication packets, which the control circuit section on the side where said determination means is provided has received from the other control circuit section or determining a state of being incapable of receiving a communication packet to be received;

said first and second adder-subtracters act as operation means that adds or subtracts a second variation value when said receiving error determination means determines the presence of error, and subtracts or adds a first variation value when the receiving error determination means determines the absence of error to perform an addition-subtraction compensation with respect to a current value memory so as to mutually counteract; and

stops an addition-subtraction compensation with said first variation value at a predetermined normal-side limit value when the determination of the absence of error continues;

said first and second error occurrence definition means act as comparison means for generating the first and second error detection signal when a current value of said adder-subtracter comes to be outside a region of a predetermined abnormal-side limit value resulted from accumulation of said first and second variation values; and

said second variation value is set to a value smaller than a permitted accumulation value, being a difference between said abnormal-side limit value and said normal-side limit value, and stopping the operation or initialization and restart of said first or second control circuit section is carried out responsive to the generation of said first and second error detection signal.

8. The electronic control unit according claim 7, wherein said first and second control circuit sections further comprise first and second initialization means;

said first initialization means acts as means that operates when said first error occurrence definition means generates the first error detection signal, resets a current value of said first adder-subtracter to a predetermined initialization value set at the start of operation, and initializes and restarts a communication control circuit section provided in said second control circuit section;

said second initialization means acts as means that operates when said second error occurrence definition means generates the second error detection signal, resets a current value of said second adder-subtracter to a predetermined initialization value set at the start of operation, and initializes and restarts a microprocessor provided in said first control circuit section, or stops the operation thereof; and

an initialization value of the first and second adder-subtracter to be reset by said first and second initialization means is a value close to said abnormal-side limit value apart from said normal-side limit value.

9. The electronic control unit according to claim 7, wherein said first and second communication error determination means further comprise at least one of bit information monitoring means, reply delay monitoring means and receiving interval monitoring means;

said bit information monitoring means acts as bit error determination means for determining the presence or absence of lack or mix in bit information such as parity check or sum check relative to a serial data communicated between said first and second control circuit sections;

said reply delay monitoring means acts as reply response error determination means for making an error determination at the control circuit section, being a source side, when a reply data from the other control circuit section in response to any data, which is transmitted by either said first or second control circuit section, cannot be received even when a predetermined reply response time period has passed;

said receiving interval monitoring means acts as receiving interval error determination means for making an error determination when a receiving interval time period at the other-side control circuit section relative to a regular transmission data that said first control circuit section transmits or a regular report data that said second control circuit section transmits, exceeds a predetermined value; and

said adder-subtracter performs an addition-subtraction compensation with a first variation value when none of said bit information monitoring means, reply delay monitoring means and receiving interval monitoring means makes an error determination.

10. The electronic control unit according to claim 9, wherein said second variation value, which said adder-subtracter adds or subtracts when the determination of said bit information monitoring means is a communication error, is a value larger than said first variation value;

a variation value, which said adder-subtracter adds or subtracts when the determination of said reply delay monitoring means or receiving interval monitoring means is a communication error, is a third variation value, being a value different from said second variation value; and

said third variation value is a value smaller than a permitted accumulation value, being a difference between said abnormal-side limit value and said normal-side limit value.

11. The electronic control unit according to claim 1, wherein said first control circuit section further comprises a direct input/output signal interface circuit, and

either said first or second control circuit section further comprises a watchdog timer and error occurrence storage means;

said direct input/output signal interface circuit is bus-connected to said microprocessor;

said microprocessor is arranged so as to generate an output signal in response to a direct input signal having been inputted via said direct input signal interface, an indirect input signal having been received by a serial communication from a second series-parallel converter provided in said second control circuit section, and a content of said program memory, thereby driving a first electrical load group, which is connected to said direct output signal interface circuit, and to transmit an indirect output signal via said first and second series-parallel converters to the second control circuit section;

said watchdog timer acts as a run-away monitoring timer circuit that monitors a watchdog clear signal, being a pulse train, which said microprocessor generates, and generates a reset pulse signal when a pulse width of said watchdog clear signal exceeds a predetermined value;

said error occurrence storage means acts as an error storage circuit that stores said first and second error detection signals or a reset pulse signal to bring annunciation means such as alarm, display, printing, and history save in operation when said error detection signals are generated and when the reset pulse signal provided by said watchdog timer is generated; and

said microprocessor is initialized and restarted when said watchdog timer generates a reset pulse signal and when said second error detection signal is generated; and

a communication control circuit section of said second control circuit section is initialized and restarted when said watchdog timer generates a reset pulse signal and when said first error detection signal is generated.

12. The electronic control unit according to claim 11, wherein said second control circuit section further comprises an auxiliary CPU, and said first control circuit section further comprises run-away monitoring means with respect to said auxiliary CPU;

said auxiliary CPU acts as a microprocessor that is contained in said second control circuit section along with an auxiliary program memory cooperating with said auxiliary CPU, an operation processing auxiliary RAM memory, an indirect input/output signal interface circuit and a second series-parallel converter, transmits to the first control circuit section via said first and second series-parallel converters an indirect input signal associated with a signal having been inputted via said indirect input signal interface circuit, and drives a second electrical load group connected to said indirect output signal interface circuit by an output associated with an indirect output signal having been received from said first control circuit section via said first and second series-parallel converters;

said run-away monitoring means is means for monitoring with a microprocessor acting as a main CPU provided in said first control circuit section a watchdog clear signal, being a pulse train that said auxiliary CPU generates, and for generating a reset pulse signal when pulse width of said watchdog clear signal exceeds a predetermined value; and

when said run-away monitoring means generates a reset pulse signal, when said watchdog timer generates a reset pulse signal and when said first error detection signal is generated, said auxiliary CPU is initialized and restarted, and said error storage circuit stores the occurrence of error.

13. The electronic control unit according to claim 11, wherein said error occurrence storage means is constituted of a count storage circuit;

and

said count storage circuit counts an OR output with respect to said first and second error detection signals and a reset pulse signal provided by the watchdog timer, and brings said annunciation means in operation when said count value reaches a predetermined value.

14. The electronic control unit according to claim 11, wherein at least one of said first and second control circuit sections further comprises driving stop means and clear means;

said driving stop means acts as a gate circuit that operates when said error occurrence storage means stores an error occurrence to inhibit driving specified electrical loads, being a part of said electrical load group; and

said clear means acts as means for initializing an error storage signal provided by said error occurrence storage means by manual operation such as turning on a power supply switch again.

15. The electronic control unit according to claim 13, wherein at least one of said first and second control circuit sections further comprises driving stop means and clear means;

said driving stop means acts as a gate circuit that operates when a count value of said count storage circuit is not less than a predetermined value to inhibit driving specified electrical loads, being a part of said electrical load group; and

said clear means acts as means for initializing a current value of said count storage circuit by manual operation such as turning on a power supply switch again.