Semiconductor circuit for arithmetic processing and arithmetic processing method
First Claim
1. A semiconductor circuit for arithmetic processing, being a semiconductor circuit receiving as input at least one numerical data item comprised of a plurality of digits, input sequentially one digit per computing time unit from the upper digit of the numerical data, provided with a computing unit for computing of the input data, the computing unit comprising:
- a computing circuit, for computing input digit data within a computing time unit, and outputting a computation result representing a result obtained by the computation to generate a carry using the computation and outputting carry data representing this carry; and
delay means for delaying the computational result from the computing circuit by only a single computing time unit.
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Abstract
There is provided a semiconductor circuit for arithmetic processing and an arithmetic processing method that can increase the rate of processing data and reduces the area of a circuit by suppressing wasteful processing.
There is provided a computing unit for computing input data, and this computing unit computes input digit data within a computation time unit and outputs a computation result representing a result obtained by the computation, and if a carry is generated in the computation a computation circuit (adders 1-3) for outputting carry data representing this carry, and delay means (memory 4) for delaying the computation result from the computation circuit by one computation time unit, are provided.
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Citations
16 Claims
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1. A semiconductor circuit for arithmetic processing, being a semiconductor circuit receiving as input at least one numerical data item comprised of a plurality of digits, input sequentially one digit per computing time unit from the upper digit of the numerical data,
provided with a computing unit for computing of the input data, the computing unit comprising: -
a computing circuit, for computing input digit data within a computing time unit, and outputting a computation result representing a result obtained by the computation to generate a carry using the computation and outputting carry data representing this carry; and
delay means for delaying the computational result from the computing circuit by only a single computing time unit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 13, 15, 16)
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11. A semiconductor circuit for arithmetic processing, comprising:
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storage means for storing a multiplier while shifting the multiplier every one computing time unit;
first computing means for respectively computing partial products of the multiplier from the storage means and an multiplicand, and generating and outputting all partial products of the same digit for multiplication sequentially from the most significant digit every computing time unit, and second computing means for adding all partial products representing the same digit from the first computing means to output one multiplication result from an upper order digit.
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12. A semiconductor circuit for arithmetic processing, receiving one of two data items as a multiplicand and the other data item as a multiplier, and sequentially inputting the multiplier every computing time unit from the upper order digit, and outputting a result of multiplying the two data items sequentially every computing time unit from an upper order digit, comprising:
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computing means for computing partial products for consecutive digits of the input multiplier and multiplicand every computing time unit;
addition means for performing addition of consecutive digits of results of adding the computed partial products of the previous computing time unit; and
means for temporarily storing addition results.
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14. An arithmetic processing method receiving input of at least one numerical data item comprised of a plurality of digits, one digit being input sequentially per computing time unit from an upper order digit of the numerical data, comprising:
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a first process of computing data of an input digit in computing time units and outputting a computation result obtained by computation;
a second process of generating a carry as a result of the computation of the first process and outputting carry data representing this carry; and
a third process of delaying the computational result by a single computing time unit.
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Specification