Semiconductor circuit for arithmetic processing and arithmetic processing method

• US 20050080835A1
• Filed: 08/15/2003
• Published: 04/14/2005
• Est. Priority Date: 12/17/1997
• Status: Active Grant

• Current Assignee: I & F Co., Ltd., Tadahiro OHMI Kabushiki Kaisha Ultraclean Technology Research Institute
• Original Assignee: I & F Co., Ltd., Tadahiro OHMI Kabushiki Kaisha Ultraclean Technology Research Institute
• Inventors: Ohmi, Tadahiro, Imai, Makoto, Kotani, Koji, Shibata, Tadashi, Fujibayashi, Masanori, Nozawa, Toshiyuki, Nitta, Takahisa
• Granted Patent: US 7,296,048 B2
• Time in Patent Office: Days
• US Class Current: 708/700
• CPC Class Codes: G06F 7/4824 using signed-digit representation
• CPC Class Codes: G06F 7/506 with simultaneous carry generation for, or propagation over, two or more stages
• CPC Class Codes: G06N 3/063 using electronic means

Abstract

There is provided a semiconductor circuit for arithmetic processing and an arithmetic processing method that can increase the rate of processing data and reduces the area of a circuit by suppressing wasteful processing.

There is provided a computing unit for computing input data, and this computing unit computes input digit data within a computation time unit and outputs a computation result representing a result obtained by the computation, and if a carry is generated in the computation a computation circuit (adders 1-3) for outputting carry data representing this carry, and delay means (memory 4) for delaying the computation result from the computation circuit by one computation time unit, are provided.

Claims

1. A semiconductor circuit for arithmetic processing, being a semiconductor circuit receiving as input at least one numerical data item comprised of a plurality of digits, input sequentially one digit per computing time unit from the upper digit of the numerical data,

provided with a computing unit for computing of the input data, the computing unit comprising:

a computing circuit, for computing input digit data within a computing time unit, and outputting a computation result representing a result obtained by the computation to generate a carry using the computation and outputting carry data representing this carry; and

delay means for delaying the computational result from the computing circuit by only a single computing time unit.

2. The semiconductor circuit for arithmetic processing of claim 1, wherein a plurality of the computing units are connected in series, and each of the computing units performs processing sequentially every computation time unit.

3. The semiconductor circuit for arithmetic processing of claim 1 or claim 2, wherein the numerical data, the computational result or the carry data belong to a redundant number system.

4. The semiconductor circuit for arithmetic processing of claim 3, wherein a computing block for computing data belonging to the redundant number system comprises at least one of the computing units and a computing circuit for processing output of the computing block, and carry data to an upper order digit is not generated from the computing block.

5. The semiconductor circuit for arithmetic processing of claim 1 or claim 2, wherein the computing unit comprises:

first decision means for deciding whether or not carry data output to an upper digit as a result of computation of a particular digit is changed using carry data generated by computation for a lower digit than that digit;

output means for indicating that there is no change to carry data to an upper order side, when a decision result from the first decision means indicates that there is no dependency on carry data output from the lower order digit;

input means for holding lower order side carry data, when the decision result from the first decision means indicates that there is dependency on carry data output from the lower order digit; and

changing means for changing a computational result in response to lower order digit carry data from the lower order side.

6. The semiconductor circuit for arithmetic processing provided of any one of claims 1 to 5, comprising decision means for comparing and deciding, every computing time unit from an upper digit, computational results output sequentially every computing time unit from the upper digit, wherein when authenticity of the decision result of the decision means has been confirmed arithmetic processing including comparison and decision for remaining lower order digits is omitted.

7. The semiconductor circuit for arithmetic processing of claim 1, claim 2 or claim 6, comprising:

computing means for sequentially carrying out computation every computing time unit from an upper digit side and computing a maximum value and a minimum value for computational results acquired at a lower digit than an input digit; and

comparison means for comparing at least one of the maximum value and the minimum value computed by the computing means with data of another digit.

8. The semiconductor circuit for arithmetic processing of claim 1 or claim 2, provided with switching means for switching a computing function for input digit data by supplying a control instruction to the computing unit.

9. The semiconductor circuit for arithmetic processing of claim 5, wherein

a computing block converts data sequentially input from an upper order digit every computing time unit to a non-redundant number system when data belongs to the redundant number system, the computing block being comprised of a plurality of computing units connected in series,

and each computing unit comprises

decision means for deciding whether or not input digit data belongs to a redundant representation and if conversion is necessary,

conversion means for converting to a non-redundant representation and a carry signal, or a borrow signal, and output means for outputting the carry signal or the borrow signal to a computing unit for an upper order digit,

the semiconductor circuit for arithmetic processing having an overall function of converting a redundant number system to a non-redundant number system.

10. The semiconductor circuit for arithmetic processing of any one of claims 1 to claim 8, further comprising, in order to convert analog data to digital data by narrowing the comparison range of the analog data, conversion means for converting the analog data sequentially every computation time unit from an upper order digit side of the digital data, and

the computing unit or the computing circuit for computing output of the conversion means every computation time unit from an upper order digit.

13. The semiconductor circuit for arithmetic processing of any one of claim 1 to claim 14, wherein the computing unit is formed using neuron MOS transistors.

15. The arithmetic processing method of claim 13, wherein from the first process to the third process is sequentially repeated.

16. The arithmetic processing method of claim 15, further comprising:

a fourth process of sequentially judging computation results of the first process from am upper order digit, and

a fifth process of suspending computation of lower order digits at a point in time where a judgement result of the fourth process is defined.

11. A semiconductor circuit for arithmetic processing, comprising:

storage means for storing a multiplier while shifting the multiplier every one computing time unit;

first computing means for respectively computing partial products of the multiplier from the storage means and an multiplicand, and generating and outputting all partial products of the same digit for multiplication sequentially from the most significant digit every computing time unit, and second computing means for adding all partial products representing the same digit from the first computing means to output one multiplication result from an upper order digit.

12. A semiconductor circuit for arithmetic processing, receiving one of two data items as a multiplicand and the other data item as a multiplier, and sequentially inputting the multiplier every computing time unit from the upper order digit, and outputting a result of multiplying the two data items sequentially every computing time unit from an upper order digit, comprising:

computing means for computing partial products for consecutive digits of the input multiplier and multiplicand every computing time unit;

addition means for performing addition of consecutive digits of results of adding the computed partial products of the previous computing time unit; and

means for temporarily storing addition results.

14. An arithmetic processing method receiving input of at least one numerical data item comprised of a plurality of digits, one digit being input sequentially per computing time unit from an upper order digit of the numerical data, comprising:

a first process of computing data of an input digit in computing time units and outputting a computation result obtained by computation;

a second process of generating a carry as a result of the computation of the first process and outputting carry data representing this carry; and

a third process of delaying the computational result by a single computing time unit.