Hardware management of JAVA threads

• US 20050080962A1
• Filed: 12/31/2002
• Published: 04/14/2005
• Est. Priority Date: 12/31/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Hsieh, Hsien-Cheng E., Penkovski, Vladimir M.
• Granted Patent: US 7,089,340 B2
• Time in Patent Office: Days
• US Class Current: 710/200
• CPC Class Codes: G06F 2209/522 Manager
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms

Abstract

A system for managing threads to handle transaction requests connected to input/output (I/O) subsystems to enable notification to threads to complete operations.

Claims

1. A computing system comprising:

a processing unit; and

a thread control processor coupled to the processing unit, the thread control processor to exclusively manage a plurality of active threads and to communicate with synchronization primitives for coordinating usage of shared resources by at least one of the plurality of active threads.

2. The computing system of claim 1, wherein one of the synchronization primitives includes a mutual exclusion object (Mutex).

3. The computing system of claim 1, wherein one of the synchronization primitives includes a Semaphore residing in storage of an operating system processed by the processing unit.

4. The computing system of claim 1, wherein the thread control processor is a co-processor.

5. The computing system of claim 1, wherein the plurality of threads supported by the thread control processor comprises at least one thread in a RUN state loaded into the processing unit.

6. The computing system of claim 5, wherein the plurality of threads supported by the thread control processor further comprises at least one thread in a WAIT state by awaiting a response one of the synchronization primitives that another thread has completed use of a shared resource.

7. The computing system of claim 6, wherein the shared resource is one of a file stored in a system memory and a operating system routine.

8. The computing system of claim 1 further comprising an input/output (I/O) device coupled to the thread control processor, the thread control processor being adapted to receive a signal to indicate completion of an I/O event form the I/O device.

9. The computing system of claim 8, wherein the I/O device is a disk controller and the I/O event is a completion of a file read operation.

10. The computing system of claim 8, wherein the I/O device is a network interface controller and the I/O event is a transmission of a message onto a network via the network interface controller.

11. A computing system comprising:

a memory to contain a synchronization primitive;

an input/output (I/O) subsystem including at least one I/O device;

a processing unit to process a control thread; and

a thread control processor coupled to the processing unit, the thread control processor to exclusively manage a plurality of active threads and to communicate with (i) the synchronization primitive via a first interconnect for coordinating usage of a shared resource by the plurality of active threads and (ii) the I/O device via a second interconnect to receive information when an I/O event by the I/O device has completed.

12. The computing system of claim 11, wherein the synchronization primitive comprises one of a mutual exclusion object (Mutex) and a Semaphore residing in the memory.

13. The computing system of claim 11, wherein the I/O device is a disk controller.

14. The computing system of claim 13, wherein the I/O event is a file read operation being completed.

15. The computing system of claim 11, wherein the I/O device is a network interface controller.

16. The computing system of claim 11, wherein the I/O event is a transmission of a message onto a network via the network interface controller.

17. A method comprising:

implementing specialized hardware in a computing system including a thread control processor;

interconnecting the thread control processor to an input/output (I/O) device and to a system memory loaded with at least one synchronization primitive;

exclusively managing a plurality of active threads by the thread control processor of the computing system.

18. The method of claim 17, wherein the exclusive managing of the plurality of active threads comprises maintaining threads until they become ready-to-run and connecting threads for operation when ready-to-run.

19. The method of claim 18, wherein the exclusive managing of the plurality of active threads further comprises selecting ready-to-run threads and connecting them to available processing resources.