Multicontext processor architecture

• US 20050081020A1
• Filed: 10/06/2004
• Published: 04/14/2005
• Est. Priority Date: 10/08/2003
• Status: Active Grant

• Current Assignee: Stmicroelectronics France (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Volp, Marcus
• Granted Patent: US 7,730,544 B2
• Time in Patent Office: Days
• US Class Current: 712/228
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence
• CPC Class Codes: G06F 2212/656 Address space sharing
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming

Abstract

A processor architecture provides for at least two simultaneous execution contexts, hardware resources having at least one execution unit, an instruction scheduler, an interrupt controller, and memory management means, and a given privileged context from among the simultaneous execution contexts that, in a privileged mode of an operating system, commands the other processor contexts by reading from and writing to registers of other contexts.

Claims

1. A processor, comprising:

at least two simultaneous execution contexts, and hardware resources comprising at least one execution unit, an instruction scheduler, an interrupt controller, and memory management means, wherein a given privileged context from among the at least two simultaneous execution contexts comprises means for restricting the use of certain at least of the hardware resources by the other execution contexts.

2. The processor of claim 1, wherein the privileged context comprises means for reading from or writing to registers of the other execution contexts.

3. The processor of claim 1, wherein the memory management means comprise two-level address translation means, having an upper directory of tables of memory pages for translating a virtual address provided as input into an intermediate address delivered as output, and a lower directory of tables of memory pages for translating an intermediate address provided as input into a physical address delivered as output, and wherein the privileged context comprises means for, in a privileged mode of the operating system, configuring said lower directory of tables of memory pages in an exclusive manner.

4. The processor of claim 3, wherein the upper directory of tables of memory pages and the lower directory of tables of memory pages share a common address translation table in which each entry is tagged by a cue indicating whether the input address is a virtual address or an intermediate address, a logic unit configured to decide whether a requested translation is available in said address translation table, and a hardware unit for walking through the memory page tables.

5. The processor of claim 3, further comprising a direct access controller for the memory that is operationally arranged between the upper directory of memory page tables and the lower directory of memory page tables.

6. The processor of claim 1, wherein the privileged context comprises means of command of the instruction scheduler, with means for interrupting and means for resuming the execution of at least one of said other execution contexts by the execution unit.

7. The processor of claim 1, wherein the privileged context comprises means of command of the interrupt controller preventing the delivery, for processing, of an interrupt instruction to one at least of said other execution contexts.

8. The processor of claim 7, wherein the interrupt controller comprises, for each interrupt request, a register having a bit associated with each of said other execution contexts, the binary value of said bit controlling the delivery or otherwise of said interrupt request to said associated context.

9. The processor of claim 8, wherein the binary value of said bit controls the selective delivery of said interrupt instruction to said associated context or to the privileged context.

10. The processor of claim 8, wherein the means of command of the interrupt controller of the privileged context comprise exclusive means for reading from and writing to said register of the interrupt controller.

22. An electronic apparatus, comprising:

a processor according to claim 1.

11. A method of managing a processor having at least two simultaneous execution contexts, and hardware resources that include at least one execution unit, an instruction scheduler, an interrupt controller, and memory management means, comprising providing a given privileged context from among the simultaneous execution contexts for restricting the use of certain at least of the hardware resources by the other execution contexts.

12. The method of claim 11, wherein the privileged context is furthermore provided for reading from and writing to the registers of the other execution contexts.

13. The method of claim 11, wherein the management of the memory comprises providing a two-level address translation having the translation of a virtual address provided as input into an intermediate address delivered as output of an upper directory of tables of memory pages, and the translation of an intermediate address provided as input into a physical address delivered as output of a lower directory of tables of memory pages, and wherein the privileged context is further provided to configure, in a privileged mode of the operating system, the lower directory of tables of memory pages in an exclusive manner.

14. The method of claim 13, wherein the upper directory of tables of memory pages and the lower directory of tables of memory pages are provided to share a common address translation table in which each entry is tagged by a cue indicating whether the input address is a virtual address or an intermediate address, and a logic unit deciding whether a requested translation is available in said address translation table, and a hardware unit for walking through the memory page tables.

15. The method of claim 13, comprising providing a direct access controller for the memory, and configuring said direct access controller for the memory to be operationally arranged between the upper directory of memory page tables and the lower directory of memory page tables.

16. The method of claim 12, wherein the privileged context is furthermore provided for commanding the instruction scheduler with an instruction for interrupting and an instruction for resuming the execution of at least one of said other execution contexts by the execution unit.

17. The method of claim 12, wherein the privileged context is furthermore provided for commanding the interrupt controller preventing the delivery to process an interrupt request to one at least of said other execution contexts.

18. The method of claim 17, comprising providing the interrupt controller for each interrupt request a register having a bit associated with each of said other execution contexts, the binary value of said bit controlling the delivery or otherwise of said interrupt request to said associated context.

19. The method of claim 18, wherein the binary value of said bit controls the selective delivery of said interrupt instruction to said associated context or to the privileged context.

20. The method of claim 18, wherein the command of the interrupt controller by the privileged context comprises reading exclusively from and the exclusive writing to said register of the interrupt controller.

21. The method of claim 11, comprising executing a process for manipulating information that is sensitive from the security point of view in the privileged context or in one of said other contexts which is encapsulated by virtue of the command by the privileged context.

23. A processor, comprising:

hardware resources that comprise at least one execution unit, an instruction scheduler, an interrupt controller, and a memory management circuit; and

at least two simultaneous execution contexts that comprise at least one given privileged context from among the simultaneous execution contexts that, in a privileged mode of operation, commands the other simultaneous execution contexts by reading from and writing to registers of the other simultaneous execution contexts.

24. A processor, comprising:

hardware resources that comprise at least one execution unit, an instruction scheduler, an interrupt controller, and a memory management circuit; and

at least two simultaneous execution contexts, wherein at least one of the at least two simultaneous execution contexts comprises a privileged context configured for restricting the use of certain of the hardware resources by the other execution contexts.

25. The processor of claim 24, wherein the privileged context comprises a circuit for reading from and writing to registers of the other execution contexts.

26. The processor of claim 24, wherein the privileged context comprises a circuit for commanding the instruction scheduler, including an interrupt circuit and a resume circuit to resume execution of at least one of the other execution contexts by the execution unit.

27. A processor, comprising:

a plurality of simultaneous execution contexts;

a privileged execution context;

a scheduler coupled to the plurality of execution contexts and to the privileged context;

an interrupt controller coupled to the plurality of execution contexts and to the privileged context;

an extraction unit having a first input coupled to an output of the scheduler, a second input coupled to a memory circuit, and an output coupled to a decoder;

a queue having an input coupled to an output of the decoder and an output coupled to a plurality of execution units, the execution units each having an output coupled to the privileged context, and at least one of the execution units having an input coupled to an output of the privileged context, the execution units further having their outputs coupled to the plurality of execution contexts; and

wherein the privileged context is configured to read from and write to registers of the plurality of execution contexts and to restrict the use of one or more of the interrupt controller, scheduler, extraction unit, memory circuit, decoder, queue, and execution units.

28. The processor of claim 27, wherein the memory circuit comprises a memory management circuit having a two-level address translation circuit comprising an upper directory of tables of memory pages for translating a virtual address provided as input into an intermediate address delivered as output, and a lower directory of tables of memory pages for translating an intermediate address provided as input into a physical address delivered as output, and wherein the privileged context is configured in a privileged mode of the operating system for configuring the lower directory of tables of memory pages in an exclusive manner.

29. The processor of claim 28, wherein the upper directory of tables of memory pages and the lower directory of tables of memory pages share a common address translation table in which each entry is tagged by a cue that indicates whether the input address is a virtual address or an intermediate address, and further comprising a logic unit configured to determine whether a requested translation is available in the address translation table.