Hybrid agent-oriented object model to provide software fault tolerance between distributed processor nodes

• US 20050081110A1
• Filed: 08/31/2004
• Published: 04/14/2005
• Est. Priority Date: 06/28/2002
• Status: Active Grant

• Current Assignee: Andy E. Rostron
• Original Assignee: Andy E. Rostron
• Inventors: Rostron, Andy E.
• Granted Patent: US 7,424,640 B2
• Time in Patent Office: Days
• US Class Current: 714/38
• CPC Class Codes: G06F 11/1489 through recovery blocks
• CPC Class Codes: G06F 11/2025 using centralised failover control functionality
• CPC Class Codes: G06F 11/2038 with a single idle spare processing component
• CPC Class Codes: G06F 11/2041 with more than one idle spare processing component

Abstract

An apparatus and method for a computer system is used for implementing an extended distributed recovery block fault tolerance scheme. The computer system includes a supervisory node, an active node and a standby node. Each of the nodes has a primary routine, an alternate routine and an acceptance test for testing the output of the routines. Each node also includes a device driver, a monitor and a node manager for determining the operational configuration of the node. The supervisory node coordinates the operation of the active and standby nodes. The primary and alternate routines are implemented with an application task through a plurality of agent objects operating as finite state machines. A reliable data link extends between the monitors of the active and standby nodes.

Claims

1-47. -47. (canceled)

48. A single bus software architecture for supporting hardware hot standby redundancy with a supervisor processing node, the improvement of adding a second supervisor processor node, alternatively in an active state, connected to said bus to thereby provide for a redundant supervisory node set.

49. The software architecture of claim 48 wherein when one of said supervisor processor nodes is in an active mode, the other supervisor processor node is in a stand-by mode.

50. The software architecture of claim 49 further comprising one or more additional busses, wherein said active supervisor processor node is attached to at least one bus and wherein said stand-by supervisor processor node is attached to at least one bus.

51. The software architecture of claim 50 wherein said active supervisor processor node and said standby supervisor processor node are attached to different busses.

52. The software architecture of claim 48 wherein said software architecture comprises a computer system.

53. The software architecture of claim 52 wherein said computer system comprises a communication system.

54. The software architecture of claim 53 wherein said communication system is a point-to-multipoint communication system.

55. The software architecture of claim 54 wherein said communication system operates in the millimeter wave frequency spectrum.

56. The computer system of claim 55 wherein said communications system is a time division multiple access system for communicating data in a frame format.

57. The computer system of claim 56 wherein the data density within each frame is dynamically variable.

58. The computer system of claim 56 wherein said communications system is a time-division duplex system.

59. The computer system of claim 58 wherein said communications system is an adaptive time division duplex system.

60. The computer system of claim 59 wherein the forward/reverse ration is dynamically configurable.