Method and test drive for detecting addressing errors in control devices

• US 20050081133A1
• Filed: 11/28/2002
• Published: 04/14/2005
• Est. Priority Date: 11/29/2001
• Status: Active Grant

• Current Assignee: Knorr-Bremse Systeme Fur Nutzfahrzeuge GMBH (Estate of Heinz Hermann Thiele)
• Original Assignee: Knorr-Bremse Systeme Fur Nutzfahrzeuge GMBH (Estate of Heinz Hermann Thiele)
• Inventors: Woerner, Dieter, Mustapha, Adnan
• Granted Patent: US 7,366,970 B2
• Time in Patent Office: Days
• US Class Current: 714/768
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06

Abstract

The invention relates to a method for detecting addressing errors in control devices of motor vehicles, whereby test data are input into all addressable memory cells by means of a present model, then read out and compared with the test data.

Claims

1-8. -8. (canceled)

9. A method of detecting addressing errors in a control unit, the method comprising the acts of:

writing preset test data of a preset model in a successive manner with respect to time into all addressable memory cells of the control unit while the control unit is deactivated by a user with respect to a normal operation;

subsequently reading out and comparing data from the addressable memory cells with the test data;

generating an error message, if applicable, as a function of the comparing act; and

wherein for all addressable memory cells, different test data are written in accordance with the preset model, and wherein the error message is stored if applicable and emitted only when the control unit is reactivated.

10. The method according to claim 9, wherein different models of test data are written in successively with respect to time.

11. The method according to claim 9, wherein the preset model is a defined byte of a respective address of the memory cells.

12. The method according to claim 10, wherein the preset model is a defined byte of a respective address of the memory cells.

13. A test device for detecting addressing errors in a control unit having an addressable memory with several individually addressable memory cells, comprising:

a test generator which writes a preset model of test data into the individually addressable memory cells;

a comparator which reads out the test data previously written into the individually addressable memory cells and compares the read out test data with the preset model of test data;

a control operably coupled to activate the test data generator when the control unit is deactivated with respect to its normal operation;

an error memory coupled to the comparator, in which faulty comparison results are stored and emitted only when the control unit is reactivated.

14. A method for detecting addressing errors in control units, the method comprising the acts of:

inputting test data into all addressable memory cells of the control unit via a preset model when the control unit is switched-off by the user;

subsequently reading out the input test data; and

comparing the subsequently read out input test data with the test data input via the preset model in order to detect any errors.

15. The method according to claim 14, wherein the preset model writes in different test data for each of the individually addressable memory cells.

16. The method according to claim 15, wherein different models of test data are written in successively with respect to time.

17. The method according to claim 14, wherein the preset model is a selected byte of a respective address of the addressable memory cells.

18. The method according to claim 14, wherein, as a function of the comparing act, an error message is generated and stored, the error message being emitted when the control unit is switched on again.

19. A test device for detecting addressing errors in a control unit having an addressable memory with several individually addressable memory cells, comprising:

a test data generator operably coupled to write into the individually addressable memory cells test data in accordance with a preset model;

a comparator operably configured to read out the previously written in test data from the individually addressable memory cells and compare the read out test data with the written in test data in accordance with the preset model in order to detect addressing errors.

20. The test device according to claim 19, further comprising a control operably configured to activate the test data generator when the control unit is switched-off.

21. The test device according to claim 19, further comprising:

an error memory coupled to the comparator, in which said error memory faulty comparison results are stored and are emitted when the control unit is switched back on via a switch.

22. The test device according to claim 20, further comprising:

an error memory coupled to the comparator, in which said error memory faulty comparison results are stored and are emitted when the control unit is switched back on via a switch.