System and method for data synchronization for a computer architecture for broadband networks

• US 20050081209A1
• Filed: 10/18/2004
• Published: 04/14/2005
• Est. Priority Date: 03/22/2001
• Status: Active Grant

• Current Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Original Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Inventors: Yamazaki, Takeshi, Suzuoki, Masakazu
• Granted Patent: US 8,028,288 B2
• Time in Patent Office: Days
• US Class Current: 718/100
• CPC Class Codes: G06F 12/1466 Key-lock mechanism
• CPC Class Codes: H04L 69/12 Protocol engines

Abstract

A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A processing system for processing computer tasks is also provided. A first processor is of a first processor type and a number of second processors are of a second processor type. One of the second processors manages process scheduling of computing tasks by providing tasks to at least one of the first and second processors.

Claims

1. A processing system for processing computing tasks, comprising:

a first processor of a first processor type; and

a plurality of second processors of a second processor type operatively connected to the first processor, a selected one of the second processors managing process scheduling of the computing tasks by providing selected ones of the computing tasks to one or more of the first processor and the plurality of second processors.