System and method for data synchronization for a computer architecture for broadband networks
First Claim
1. A processing system, comprising:
- a plurality of processing devices capable of processing tasks; and
an absolute timer defining a time budget for use by selected ones of the processing devices;
wherein the time budget provides a time period for the completion of one or more of the tasks by the selected processing devices independent of frequencies of clocks employed by the selected processing devices for processing the one or more tasks.
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Abstract
A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A processing system for processing tasks is also provided. The processing system includes processing devices and an absolute timer. The absolute timer defines a time budget. The time budget provides a time period for the completion of tasks by selected processing devices independent of clock frequencies employed by the processing devices for processing the tasks.
313 Citations
1 Claim
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1. A processing system, comprising:
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a plurality of processing devices capable of processing tasks; and
an absolute timer defining a time budget for use by selected ones of the processing devices;
wherein the time budget provides a time period for the completion of one or more of the tasks by the selected processing devices independent of frequencies of clocks employed by the selected processing devices for processing the one or more tasks.
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Specification