Platinum stuffed with silicon oxide as a diffusion oxygen barrier for semiconductor devices

• US 20050082587A1
• Filed: 08/30/2004
• Published: 04/21/2005
• Est. Priority Date: 08/29/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Marsh, Eugene P.
• Granted Patent: US 7,157,783 B2
• Time in Patent Office: Days
• US Class Current: 257/296
• CPC Class Codes: H01L 21/28562 Selective deposition
• CPC Class Codes: H01L 21/7687 Thin films associated with contacts of capacitors
• CPC Class Codes: H01L 28/65 comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
• CPC Class Codes: H01L 28/75 comprising two or more layers, e.g. comprising a barrier layer and a metal layer
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H10B 12/0335 Making a connection between the transistor and the capacitor, e.g. plug
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
• CPC Class Codes: H10B 53/30 characterised by the memory core region

Abstract

The present invention provides techniques to fabricate high dielectric MIM storage cell capacitors. In one embodiment, this is accomplished by forming a silicon contact is then formed to electrically connect the formed bottom electrode layer in the container with the at least one associated transistor device. A titanium nitride barrier layer is then formed over the silicon contact. An oxygen barrier layer including platinum stuffed with silicon oxide is then formed over the titanium nitride layer and below the bottom electrode layer. A bottom electrode layer is then formed using platinum over interior surfaces of a container formed relative to at lest one associated transistor device on a silicon substrate. Further, a high dielectric insulator layer is formed over the bottom electrode layer. A top electrode layer is then formed over the high dielectric insulator layer.

Claims

1. A semiconductor structure including a high dielectric MIM container capacitor and at least one associated transistor device, on a silicon substrate, comprising:

a cup-shaped bottom electrode defining an interior surface and an exterior surface within a container formed on the silicon substrate, wherein the bottom electrode comprises platinum;

a high dielectric layer overlying the interior surface of the bottom electrode;

a top electrode overlying the high dielectric layer; and

a polysilicon contact electrically connecting the bottom electrode with the silicon substrate, wherein the polysilicon contact includes a titanium nitride barrier layer overlying the polysilicon contact, and platinum stuffed with silicon oxide barrier layer overlying the titanium nitride layer and underlying the bottom electrode.

2. The semiconductor structure of claim 1, wherein forming the high dielectric insulator layer further comprises:

annealing the formed high dielectric insulator layer to temperatures of about 450°

C. to 850°

C. in an oxygen-containing atmosphere.

3. The semiconductor structure of claim 1, wherein the oxygen barrier layer is about 50 to 5000 Å

thick.

4. The semiconductor structure of claim 1, wherein the TiN barrier layer is about 50 to 1000 Å

thick.

5. A semiconductor structure including a high dielectric MIM container capacitor and at least one associated transistor device, on a silicon substrate, comprising:

a cup-shaped bottom electrode defining an interior surface and an exterior surface within a container formed on the silicon substrate, wherein the bottom electrode comprises rhodium;

a high dielectric layer overlying the interior surface of the bottom electrode;

a top electrode overlying the high dielectric layer; and

a polysilicon contact electrically connecting the bottom electrode with the silicon substrate, wherein the polysilicon contact includes a titanium nitride barrier layer overlying the polysilicon contact, and rhodium stuffed with silicon oxide barrier layer overlying the titanium nitride layer and underlying the bottom electrode.

6. The semiconductor structure of claim 5, wherein the high dielectric layer comprises:

a tantalum oxide layer formed by annealing the tantalum oxide layer to temperatures in the range of about 450°

C. to 850°

C. in an oxygen-containing atmosphere.

7. The semiconductor structure of claim 5, wherein the oxygen barrier layer is about 50 to 5000 Å

thick.

8. The semiconductor structure of claim 5, wherein the tantalum oxide layer is about 50 to 150 Å

thick.

9. A semiconductor structure including a high dielectric MIM container capacitor and at least one associated transistor device, on a silicon substrate, comprising:

a cup-shaped bottom electrode defining an interior surface and an exterior surface within a container formed on the silicon substrate, wherein the bottom electrode comprises iridium;

a high dielectric layer overlying the interior surface of the bottom electrode;

a top electrode overlying the high dielectric layer; and

a polysilicon contact electrically connecting the bottom electrode with the silicon substrate, wherein the polysilicon contact includes a titanium nitride barrier layer overlying the polysilicon contact, and iridium stuffed with silicon oxide barrier layer overlying the titanium nitride layer and underlying the bottom electrode.

10. The semiconductor structure of claim 9, wherein the high dielectric layer comprises:

a tantalum oxide layer formed by annealing the tantalum oxide layer to temperatures in the range of about 450°

C. to 850°

C. in an oxygen-containing atmosphere.

11. The semiconductor structure of claim 9, wherein the oxygen barrier layer is about 50 to 5000 Å

thick.

12. The semiconductor structure of claim 9, wherein the tantalum oxide layer is about 50 to 150 Å

thick.

13. A high dielectric MIM storage cell capacitor, comprising:

a silicon substrate;

an oxygen barrier layer including silicon oxide doped platinum overlying the silicon substrate;

a bottom platinum electrode layer overlying the oxygen barrier layer;

a high dielectric layer overlying the bottom platinum electrode layer; and

a top electrode overlying the high dielectric layer.

14. The capacitor of claim 13, wherein the high dielectric layer comprises a tantalum oxide layer formed by annealing to temperatures in the range of about 450°

C. to 850°

C. in an oxygen-containing atmosphere.

15. The capacitor of claim 13, wherein the oxygen barrier layer is about 50 to 5000 Å

thick.

16. The capacitor of claim 13, wherein the tantalum oxide layer is about 50 to 150 Å

thick.

17. A semiconductor structure including a high dielectric MIM container capacitor and at least one associated transistor device, on a silicon substrate, comprising:

a cup-shaped bottom electrode defining an interior surface and an exterior surface within a container formed on the silicon substrate;

a high dielectric layer overlying the interior surface of the bottom electrode;

a top electrode overlying the high dielectric layer; and

a polysilicon contact electrically connecting the bottom electrode with the silicon substrate, wherein the polysilicon contact includes a titanium nitride barrier layer overlying the polysilicon contact, and iridium stuffed with silicon oxide barrier layer overlying the titanium nitride layer and underlying the bottom electrode.

18. The semiconductor structure of claim 17, wherein the high dielectric layer comprises:

a tantalum oxide layer formed by annealing the tantalum oxide layer to temperatures in the range of about 450°

C. to 850°

C. in an oxygen-containing atmosphere.

19. The semiconductor structure of claim 17, wherein the oxygen barrier layer is about 50 to 5000 Å

thick.

20. A semiconductor structure including a high dielectric MIM container capacitor and at least one associated transistor device, on a silicon substrate, comprising:

a cup-shaped bottom electrode defining an interior surface and an exterior surface within a container formed on the silicon substrate, wherein the bottom electrode comprises a noble metal;

a high dielectric layer overlying the interior surface of the bottom electrode;

a top electrode overlying the high dielectric layer; and

a polysilicon contact electrically connecting the bottom electrode with the silicon substrate, wherein the polysilicon contact includes a titanium nitride barrier layer overlying the polysilicon contact, and a noble metal stuffed with silicon oxide barrier layer overlying the titanium nitride layer and underlying the bottom electrode.

21. The semiconductor structure of claim 20, wherein the high dielectric layer comprises:

a tantalum oxide layer formed by annealing the tantalum oxide layer to temperatures in the range of about 450°

C. to 850°

C. in an oxygen-containing atmosphere.

22. The semiconductor structure of claim 20, wherein the oxygen barrier layer is about 50 to 5000 Å

thick.

23. The semiconductor structure of claim 20, wherein the noble metal is selected from the group consisting of platinum, iridium, and rhodium.

24. A semiconductor device, comprising:

a silicon substrate;

an oxygen barrier layer including platinum stuffed with silicon oxide overlying the silicon substrate;

a bottom platinum electrode layer overlying the oxygen barrier layer;

a tantalum oxide dielectric layer overlying the bottom platinum electrode layer; and

a top electrode overlying the tantalum oxide dielectric layer.

25. The semiconductor device e of claim 24, wherein the tantalum oxide layer is deposited by annealing the tantalum oxide layer to temperatures in the range of about 450°

C. to 850°

C. in an oxygen-containing atmosphere.

26. The semiconductor device of claim 24, wherein the oxygen barrier layer is about 50 to 5000 Å

thick.

27. A semiconductor structure, comprising:

a plurality of semiconductor devices, wherein each semiconductor device including at least one transistor device, in a silicon substrate comprises;

a cup-shaped bottom electrode defining an interior surface and an exterior surface within a container formed in the silicon substrate, wherein the bottom electrode is made of platinum;

a high dielectric layer overlying the interior surface of the bottom electrode;

a top electrode overlying the high dielectric layer; and

a polysilicon contact electrically connecting the bottom electrode with the at least one transistor device, wherein the polysilicon contact includes a titanium nitride barrier layer and a platinum stuffed with silicon oxide barrier layer overlying the polysilicon contact and underlying the bottom electrode.

28. The semiconductor structure of claim 27, wherein the high dielectric layer comprises materials selected from the group consisting of tantalum oxide (Ta₂O₅), strontium titanate (SrTiO₃), alumina (Al₂O₃), hafnium oxide (HfO₂), titanium oxide (TiO₂), zirconium oxide (ZrO₂), barium strontium titanate BaSrTiO₃ (BST).

29. The semiconductor structure of claim 27, wherein the platinum stuffed with silicon oxide barrier layer is about 50 to 5000 Å

thick.

30. The semiconductor structure of claim 27, wherein the high dielectric layer is about 50 to 150 Å

thick.

31. A logic circuit, comprising:

a plurality of semiconductor devices, wherein each semiconductor device includes at least one transistor device in a silicon substrate comprises;

a cup-shaped bottom platinum electrode defining an interior surface and an exterior surface within a container formed in the silicon substrate;

a high dielectric layer overlying the interior surface of the bottom electrode;

a top electrode overlying the high dielectric layer; and

a silicon contact, including a titanium nitride barrier layer and a platinum stuffed with silicon oxide barrier layer overlying the silicon contact and underlying the bottom electrode, electrically connects the bottom electrode with the at least one transistor device.

32. The logic circuit of claim 31, wherein the transistor device is disposed over an active region surrounded by an isolation region in the silicon substrate.

33. The logic circuit of claim 31, wherein the transistor device comprises:

a gate oxide layer over the active region; and

a gate electrode stack over the gate oxide layer.

34. The logic circuit of claim 31, wherein the platinum stuffed with silicon oxide barrier layer is about 50 to 5000 Å

thick.

35. The logic circuit of claim 31, wherein the silicon contact is a polysilicon contact.

36. A semiconductor device, comprising:

a plurality of high dielectric MIM storage cell capacitors, wherein each capacitor comprises;

an oxygen barrier layer, including platinum stuffed with silicon oxide overlying a silicon substrate;

a bottom platinum electrode layer overlying the oxygen barrier layer;

a tantalum oxide dielectric layer overlying the bottom platinum electrode layer; and

a top electrode overlying the tantalum oxide dielectric layer.

37. The semiconductor device of claim 36, wherein the top electrode is made from platinum.

38. A semiconductor structure including a high dielectric MIM container capacitor on a silicon substrate, comprising:

a cup-shaped bottom electrode defining an interior surface and an exterior surface within a container formed on the silicon substrate, wherein the bottom electrode comprises platinum;

a high dielectric layer overlying the interior surface of the bottom electrode;

a top electrode overlying the high dielectric layer; and

a polysilicon contact electrically connecting the bottom electrode with a buried electrical contact on the silicon substrate;

wherein the polysilicon contact includes a titanium nitride barrier layer overlying the polysilicon contact, and platinum stuffed with silicon oxide barrier layer overlying the titanium nitride layer and underlying the bottom electrode.

39. The semiconductor structure of claim 38, wherein forming the high dielectric insulator layer further comprises:

annealing the formed high dielectric insulator layer to temperatures of about 450°

C. to 850°

C. in an oxygen-containing atmosphere.

40. The semiconductor structure of claim 38, wherein the oxygen barrier layer is about 50 to 5000 Å

thick.