Platinum stuffed with silicon oxide as a diffusion oxygen barrier for semiconductor devices
First Claim
1. A semiconductor structure including a high dielectric MIM container capacitor and at least one associated transistor device, on a silicon substrate, comprising:
- a cup-shaped bottom electrode defining an interior surface and an exterior surface within a container formed on the silicon substrate, wherein the bottom electrode comprises platinum;
a high dielectric layer overlying the interior surface of the bottom electrode;
a top electrode overlying the high dielectric layer; and
a polysilicon contact electrically connecting the bottom electrode with the silicon substrate, wherein the polysilicon contact includes a titanium nitride barrier layer overlying the polysilicon contact, and platinum stuffed with silicon oxide barrier layer overlying the titanium nitride layer and underlying the bottom electrode.
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Accused Products
Abstract
The present invention provides techniques to fabricate high dielectric MIM storage cell capacitors. In one embodiment, this is accomplished by forming a silicon contact is then formed to electrically connect the formed bottom electrode layer in the container with the at least one associated transistor device. A titanium nitride barrier layer is then formed over the silicon contact. An oxygen barrier layer including platinum stuffed with silicon oxide is then formed over the titanium nitride layer and below the bottom electrode layer. A bottom electrode layer is then formed using platinum over interior surfaces of a container formed relative to at lest one associated transistor device on a silicon substrate. Further, a high dielectric insulator layer is formed over the bottom electrode layer. A top electrode layer is then formed over the high dielectric insulator layer.
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Citations
40 Claims
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1. A semiconductor structure including a high dielectric MIM container capacitor and at least one associated transistor device, on a silicon substrate, comprising:
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a cup-shaped bottom electrode defining an interior surface and an exterior surface within a container formed on the silicon substrate, wherein the bottom electrode comprises platinum;
a high dielectric layer overlying the interior surface of the bottom electrode;
a top electrode overlying the high dielectric layer; and
a polysilicon contact electrically connecting the bottom electrode with the silicon substrate, wherein the polysilicon contact includes a titanium nitride barrier layer overlying the polysilicon contact, and platinum stuffed with silicon oxide barrier layer overlying the titanium nitride layer and underlying the bottom electrode. - View Dependent Claims (2, 3, 4)
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5. A semiconductor structure including a high dielectric MIM container capacitor and at least one associated transistor device, on a silicon substrate, comprising:
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a cup-shaped bottom electrode defining an interior surface and an exterior surface within a container formed on the silicon substrate, wherein the bottom electrode comprises rhodium;
a high dielectric layer overlying the interior surface of the bottom electrode;
a top electrode overlying the high dielectric layer; and
a polysilicon contact electrically connecting the bottom electrode with the silicon substrate, wherein the polysilicon contact includes a titanium nitride barrier layer overlying the polysilicon contact, and rhodium stuffed with silicon oxide barrier layer overlying the titanium nitride layer and underlying the bottom electrode. - View Dependent Claims (6, 7, 8)
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9. A semiconductor structure including a high dielectric MIM container capacitor and at least one associated transistor device, on a silicon substrate, comprising:
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a cup-shaped bottom electrode defining an interior surface and an exterior surface within a container formed on the silicon substrate, wherein the bottom electrode comprises iridium;
a high dielectric layer overlying the interior surface of the bottom electrode;
a top electrode overlying the high dielectric layer; and
a polysilicon contact electrically connecting the bottom electrode with the silicon substrate, wherein the polysilicon contact includes a titanium nitride barrier layer overlying the polysilicon contact, and iridium stuffed with silicon oxide barrier layer overlying the titanium nitride layer and underlying the bottom electrode. - View Dependent Claims (10, 11, 12)
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13. A high dielectric MIM storage cell capacitor, comprising:
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a silicon substrate;
an oxygen barrier layer including silicon oxide doped platinum overlying the silicon substrate;
a bottom platinum electrode layer overlying the oxygen barrier layer;
a high dielectric layer overlying the bottom platinum electrode layer; and
a top electrode overlying the high dielectric layer. - View Dependent Claims (14, 15, 16)
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17. A semiconductor structure including a high dielectric MIM container capacitor and at least one associated transistor device, on a silicon substrate, comprising:
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a cup-shaped bottom electrode defining an interior surface and an exterior surface within a container formed on the silicon substrate;
a high dielectric layer overlying the interior surface of the bottom electrode;
a top electrode overlying the high dielectric layer; and
a polysilicon contact electrically connecting the bottom electrode with the silicon substrate, wherein the polysilicon contact includes a titanium nitride barrier layer overlying the polysilicon contact, and iridium stuffed with silicon oxide barrier layer overlying the titanium nitride layer and underlying the bottom electrode. - View Dependent Claims (18, 19)
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20. A semiconductor structure including a high dielectric MIM container capacitor and at least one associated transistor device, on a silicon substrate, comprising:
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a cup-shaped bottom electrode defining an interior surface and an exterior surface within a container formed on the silicon substrate, wherein the bottom electrode comprises a noble metal;
a high dielectric layer overlying the interior surface of the bottom electrode;
a top electrode overlying the high dielectric layer; and
a polysilicon contact electrically connecting the bottom electrode with the silicon substrate, wherein the polysilicon contact includes a titanium nitride barrier layer overlying the polysilicon contact, and a noble metal stuffed with silicon oxide barrier layer overlying the titanium nitride layer and underlying the bottom electrode. - View Dependent Claims (21, 22, 23)
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24. A semiconductor device, comprising:
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a silicon substrate;
an oxygen barrier layer including platinum stuffed with silicon oxide overlying the silicon substrate;
a bottom platinum electrode layer overlying the oxygen barrier layer;
a tantalum oxide dielectric layer overlying the bottom platinum electrode layer; and
a top electrode overlying the tantalum oxide dielectric layer. - View Dependent Claims (25, 26)
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27. A semiconductor structure, comprising:
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a plurality of semiconductor devices, wherein each semiconductor device including at least one transistor device, in a silicon substrate comprises;
a cup-shaped bottom electrode defining an interior surface and an exterior surface within a container formed in the silicon substrate, wherein the bottom electrode is made of platinum;
a high dielectric layer overlying the interior surface of the bottom electrode;
a top electrode overlying the high dielectric layer; and
a polysilicon contact electrically connecting the bottom electrode with the at least one transistor device, wherein the polysilicon contact includes a titanium nitride barrier layer and a platinum stuffed with silicon oxide barrier layer overlying the polysilicon contact and underlying the bottom electrode. - View Dependent Claims (28, 29, 30)
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31. A logic circuit, comprising:
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a plurality of semiconductor devices, wherein each semiconductor device includes at least one transistor device in a silicon substrate comprises;
a cup-shaped bottom platinum electrode defining an interior surface and an exterior surface within a container formed in the silicon substrate;
a high dielectric layer overlying the interior surface of the bottom electrode;
a top electrode overlying the high dielectric layer; and
a silicon contact, including a titanium nitride barrier layer and a platinum stuffed with silicon oxide barrier layer overlying the silicon contact and underlying the bottom electrode, electrically connects the bottom electrode with the at least one transistor device. - View Dependent Claims (32, 33, 34, 35)
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36. A semiconductor device, comprising:
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a plurality of high dielectric MIM storage cell capacitors, wherein each capacitor comprises;
an oxygen barrier layer, including platinum stuffed with silicon oxide overlying a silicon substrate;
a bottom platinum electrode layer overlying the oxygen barrier layer;
a tantalum oxide dielectric layer overlying the bottom platinum electrode layer; and
a top electrode overlying the tantalum oxide dielectric layer. - View Dependent Claims (37)
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38. A semiconductor structure including a high dielectric MIM container capacitor on a silicon substrate, comprising:
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a cup-shaped bottom electrode defining an interior surface and an exterior surface within a container formed on the silicon substrate, wherein the bottom electrode comprises platinum;
a high dielectric layer overlying the interior surface of the bottom electrode;
a top electrode overlying the high dielectric layer; and
a polysilicon contact electrically connecting the bottom electrode with a buried electrical contact on the silicon substrate;
wherein the polysilicon contact includes a titanium nitride barrier layer overlying the polysilicon contact, and platinum stuffed with silicon oxide barrier layer overlying the titanium nitride layer and underlying the bottom electrode. - View Dependent Claims (39, 40)
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Specification