Memory cell and method for forming the same

• US 20050082594A1
• Filed: 11/09/2004
• Published: 04/21/2005
• Est. Priority Date: 06/21/2002
• Status: Active Grant

• Current Assignee: Nanya Technology Corporation
• Original Assignee: Kris K. Brown
• Inventors: Brown, Kris K.
• Granted Patent: US 7,034,351 B2
• Time in Patent Office: Days
• US Class Current: 257/306
• CPC Class Codes: H01L 28/90 having vertical extensions
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor

Abstract

A semiconductor memory cell structure and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, an epitaxial post formed on the surface of the substrate over the active region. The epitaxial post has at least one surface extending outwardly from the surface of the substrate and another surface opposite of the surface of the substrate. A gate structure is formed adjacent to at least a portion of all the outwardly extending surfaces of the epitaxial post, and a capacitor formed on an exposed surface of the epitaxial post.

Claims

1-77. -77. (canceled)

78. A computer system, comprising:

a processor having a processor bus;

an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system;

an output device coupled to the processor through the processor bus and adapted to allow data to be output from the computer system; and

a memory device coupled to the processor through the processor bus, the memory device comprising;

an array of memory cells formed on a substrate including silicon, the memory cells arranged in rows and columns, each of the rows having a word line and each of the columns having a bit line;

a row address circuit coupled to the address bus for activating the word line in the array corresponding to a row address applied to the row address circuit through the address bus;

a column address circuit coupled to the address bus for coupling an I/O line for the array to the bit line corresponding to a column address applied to the column address circuit through the address bus; and

a sense amplifier having an input coupled to a data line and an output coupled to the data terminal of the memory device, wherein each memory cell comprises;

an active region formed in the substrate;

an epitaxial post formed on a surface of the substrate over the active region, the epitaxial post defined by at least one surface facing away from the surface of the substrate and at least two peripheral surfaces;

a transfer gate formed adjacent to the at least two peripheral surfaces of the epitaxial post; and

a memory cell capacitor formed on an exposed surface of the epitaxial post.

79. The computer system of claim 78, wherein the memory cells of the memory device further comprise an insulating layer formed over the at least two peripheral surfaces.

80. The computer system of claim 78, wherein the transfer gate of the memory device comprises:

a gate oxide formed on the at least two peripheral surfaces of the epitaxial post; and

a polysilicon gate formed on the gate oxide.

81. The computer system of claim 78, wherein the memory cells of the memory device further comprise:

a insulating layer formed over the active region;

an opening through the insulating layer to expose a portion of the active region; and

a conductive material formed in the opening and on the active region to be electrically coupled thereto.

82. The computer system of claim 78, wherein the memory cells of the memory device further comprise an insulating material formed over the transfer gate to electrically insulate the transfer gate.

83. The computer system of claim 78, wherein the active region of the memory device comprises a buried digit line.

84. The computer system of claim 78, wherein the memory cell capacitor of the memory device comprises a container shaped capacitor structure.

85. The computer system of claim 78, wherein the epitaxial post of the memory device comprises an epitaxial post having a polygonal cross-sectional area.

86. The memory device of claim 78, wherein the transfer gate extends peripherally about the epitaxial post.

87. The memory device of claim 78, wherein the epitaxial post comprises a channel region.