Low K dielectric integrated circuit interconnect structure

• US 20050082606A1
• Filed: 10/20/2003
• Published: 04/21/2005
• Est. Priority Date: 10/20/2003
• Status: Abandoned Application

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Grunow, Stephan, Papa Rao, Satyavolu S., Russell, Noel M.
• Application Number:
  US10/689,348
• Publication Number:
  US 20050082606A1
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/02115 the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
• CPC Class Codes: H01L 21/02118 carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC polymers per se C08G, photoresist per se G03F
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/02131 the material being halogen doped silicon oxides, e.g. FSG
• CPC Class Codes: H01L 21/02134 the material comprising hydrogen silsesquioxane, e.g. HSQ
• CPC Class Codes: H01L 21/02137 the material comprising alkyl silsesquioxane, e.g. MSQ
• CPC Class Codes: H01L 21/02203 the layer being porous
• CPC Class Codes: H01L 21/3124 layers comprising hydrogen silsesquioxane
• CPC Class Codes: H01L 21/3127 Layers comprising fluoro (hydro)carbon compounds, e.g. polytetrafluoroethylene
• CPC Class Codes: H01L 21/3146 Carbon layers, e.g. diamond-like layers
• CPC Class Codes: H01L 21/31629 Deposition of halogen doped silicon oxide, e.g. fluorine doped silicon oxide
• CPC Class Codes: H01L 21/31695 Deposition of porous oxides or porous glassy oxides or oxide based porous glass
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76865 Selective removal of parts of the layer H01L21/76844 takes precedence
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A Low K dielectric layer (20) is formed over a semiconductor (10). Trenches (110, 120) are formed in the dielectric layer (2) and a barrier layer (70) is formed in the trenches. The barrier layer has a thickness of X₁ over the upper surface of the dielectric layer and X₂ on the sidewalls of the trenches where X₁ is greater than X₂. A second barrier layer (130) can be formed over the first barrier layer (70) and copper (100) is formed over both barrier layers to fill the trench.

Claims

1. An integrated circuit interconnect structure, comprising:

a low K dielectric layer with an upper surface formed over a semiconductor;

a first trench formed in said low K dielectric layer wherein said trench has sidewalls;

a first contiguous barrier layer formed to a thickness X₁ over said upper surface of said low k dielectric layer and formed to a thickness X₂ on said trench sidewalls wherein X₁ is greater than X₂; and

copper formed over said first contiguous barrier.

2. The integrated circuit interconnect structure of claim 1 further comprising a second trench comprising sidewalls formed in said low K dielectric layer and separated from said first trench by a distance less than 160 nm.

3. The integrated circuit interconnect structure of claim 2 wherein said first contiguous barrier layer is formed to a thickness X₂ on said trench sidewalls of said second trench.

4. The integrated circuit interconnect structure of claim 1 wherein the ratio X₁ to X₂ is greater than 3 to 2.

5. The integrated circuit interconnect structure of claim 3 wherein the ratio X₁ to X₂ is greater than 3 to 2.

6. The integrated circuit of claim 1 further comprising a second contiguous barrier layer formed over said first contiguous barrier layer and beneath said copper.

7. A copper integrated circuit interconnect structure, comprising:

a low K dielectric layer with an upper surface formed over a semiconductor;

a plurality of trenches formed in said low K dielectric layer wherein said plurality of trenches has sidewalls;

a first contiguous barrier layer formed to a thickness X₁ over said upper surface of said low k dielectric layer and formed to a thickness X₂ over said sidewalls of said plurality of trenches wherein the ratio of X₁ to X₂ is greater than 3 to 2; and

copper formed over said first contiguous barrier.

8. The integrated circuit interconnect structure of claim 7 wherein said plurality of trenches are separated from each other by a distance of less than 160 nm.

9. The integrated circuit interconnect structure of claim 7 further comprising a second contiguous barrier layer formed over said first contiguous barrier layer and beneath said copper.

10. The interconnect structure of claim 7 wherein the dielectric constant of the low K dielectric layer is less than or equal to approximately 3.7.

11. A method for forming a copper interconnect structure, comprising:

forming a low K dielectric layer with an upper surface over a semiconductor;

forming a plurality of trenches in said low K dielectric layer wherein said plurality of trenches has sidewalls;

forming a first contiguous barrier layer to a thickness X₁ over said upper surface of said low k dielectric layer and to a thickness X₂ over said sidewalls of said plurality of trenches wherein the ratio of X₁ to X₂ is greater than 3 to 2; and

forming copper over said first contiguous barrier.

12. The method of claim 11 wherein said plurality of trenches are separated from each other by a distance of less than 160 nm.

13. The method of claim 12 further comprising forming a second contiguous barrier layer over said first contiguous barrier layer and beneath said copper.

14. The method of claim 13 wherein the dielectric constant of the low K dielectric layer is less than or equal to approximately 3.7.

15. A method for forming an integrated circuit copper interconnect structure, comprising:

forming a low K dielectric layer with a dielectric constant less than or equal to approximately 3.7 with an upper surface over a semiconductor;

forming a plurality of trenches separated by a distance of less than 160 nm in said low K dielectric layer wherein said plurality of trenches has sidewalls;

forming a first contiguous barrier layer to a thickness X₁ over said upper surface of said low k dielectric layer and to a thickness X₂ over said sidewalls of said plurality of trenches wherein the ratio of X₁ to X₂ is greater than 3 to 2; and

forming copper over said first contiguous barrier.

16. The method of claim 15 further comprising forming a second contiguous barrier layer over said first contiguous barrier layer and beneath said copper.