HIGH PERFORMANCE STRAINED CMOS DEVICES

• US 20050082634A1
• Filed: 10/16/2003
• Published: 04/21/2005
• Est. Priority Date: 10/16/2003
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Doris, Bruce B., Gluschenkov, Oleg G.
• Granted Patent: US 7,119,403 B2
• Time in Patent Office: Days
• US Class Current: 257/510
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7846 the means being located in the lateral device isolation region, e.g. STI

Abstract

A semiconductor device and method of manufacture provide an n-channel field effect transistor (nFET) having a shallow trench isolation with overhangs that overhang Si-SiO₂ interfaces in a direction parallel to the direction of current flow and in a direction transverse to current flow. The device and method also provide a p-channel field effect transistor (pFET) having a shallow trench isolation with an overhang that overhangs Si-SiO₂ interfaces in a direction transverse to current flow. However, the shallow trench isolation for the pFET is devoid of overhangs, in the direction parallel to the direction of current flow.

Claims

1. A semiconductor structure formed on a substrate, comprising a shallow trench isolation having at least one overhang selectively configured to prevent oxidation induced stress in a determined portion of the substrate, and wherein one of the at least one overhang is selectively configured to prevent oxidation induced stress in a direction parallel to or transverse to a direction of a current flow.

4. The semiconductor structure of claim 1, wherein:

the determined portion of the substrate is an Si-SiO₂ interface adjacent to the shallow trench isolation; and

the at least one overhang extends beyond the Si-SiO₂ interface, preventing oxidation at or near the Si-SiO₂ interface.

5. The semiconductor structure of claim 1, further comprising:

a first device having a source and a drain with a direction of current flow for the first device; and

a second device having a source and drain with a direction of current flow for the second device;

wherein the shallow trench isolation includes;

a first shallow trench isolation side for the first device having at least one overhang configured to prevent oxidation induced stress in a direction parallel to the direction of current flow for the first device; and

a second shallow trench isolation side for the first device having at least one overhang configured to prevent oxidation induced stress in a direction transverse to the direction of current flow for the first device; and

a third shallow trench isolation side for the second device having at least one overhang configured to prevent oxidation induced stress in a direction transverse to the direction of current flow for the first device.

6. The semiconductor structure of claim 5, wherein the shallow trench isolation further includes a fourth shallow trench isolation side for the second device, the fourth shallow trench isolation being devoid of an overhang.

12. The semiconductor structure of claim 1, wherein the overhang includes a T-shaped structure.

13. The semiconductor structure of claim 12, wherein the determined portion of the substrate is an Si-SiO₂ interface adjacent to the shallow trench isolation.

14. The semiconductor structure of claim 13, wherein the overhang includes a horizontal portion that extends beyond the Si-SiO₂ interface by about 0.01 microns to 0.5 microns.

2-3. -3. (canceled)

7. A semiconductor structure formed on a substrate, comprising:

an n-channel field effect transistor having a source, a drain, a gate, and a direction of current flow from the source to the drain; and

a first shallow trench isolation for the n-channel field effect transistor, the first shallow trench isolation having a first shallow trench isolation side, the first shallow trench isolation side having at least one overhang configured to prevent oxidation induced stress in a direction parallel to the direction of current flow for the n-channel field effect transistor.

8. The semiconductor structure of claim 7, wherein the first shallow trench isolation for the n-channel field effect transistor further comprises:

a second shallow trench isolation side being transverse to the first shallow trench isolation side and having at least one overhang configured to prevent oxidation induced stress in a direction transverse to the direction of current flow for the n-channel field effect transistor.

9. The semiconductor structure of claim 8, further comprising:

a p-channel field effect transistor, the p-channel field effect transistor having a source, a drain, a gate, and a direction of current flow from the source to the drain;

a second shallow trench isolation for the p-channel field effect transistor having a third shallow trench isolation side, the third shallow trench isolation side being devoid of an overhang; and

the second shallow trench isolation for the p-channel field effect transistor further having a fourth shallow trench isolation side, the fourth shallow trench isolation side being transverse to the third shallow trench isolation side and having at least one overhang configured to prevent oxidation induced stress in a direction transverse to the direction of current flow for the p-channel field effect transistor.

10. The semiconductor structure of claim 9, wherein the overhang configured to prevent oxidation induced stress in a direction transverse to the direction of current flow prevents a degradation of hole mobility.

11. The semiconductor structure of claim 9, wherein:

the distance from the gate of the n-channel field effect transistor to the first shallow trench isolation side of the first shallow trench isolation for the n-channel field effect transistor is less than or equal to a distance within which oxidation induced stress adjacent to the first shallow trench isolation would affect performance of the n-channel field effect transistor, and

the distance from the gate of the n-channel field effect transistor to the second shallow trench isolation side of the first shallow trench isolation for the n-channel field effect transistor is less than or equal to a distance within which oxidation induced stress adjacent to the second shallow trench isolation would affect performance of the n-channel field effect transistor.

15. The semiconductor structure of claim 9, wherein the distance from the gate of the p-channel field effect transistor to the fourth shallow trench isolation side for the second shallow trench isolation for the p-channel field effect transistor is less than or equal to a distance within which oxidation induced stress adjacent to the fourth shallow trench isolation side would affect performance of the p-channel field effect transistor.

16. The semiconductor structure of claim 15, wherein the distance from the gate of the p-channel field effect transistor to the fourth shallow trench isolation side is less than or equal to about 5.0 microns.

17. The semiconductor structure of claim 11, wherein the distance from the gate of the n-channel field effect transistor to the first shallow trench isolation side is less than or equal to about 5.0 microns.

18. The semiconductor structure of claim 11, wherein the distance from the gate of the n-channel field effect transistor to the second shallow trench isolation side is less than or equal to about 5.0 microns.

19-22. -22. (canceled)