Rail-to-rail-input buffer
1 Assignment
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Accused Products
Abstract
Rail-to-rail-Input Buffer with constant mutual conductance comprising a differential input having a first input terminal and a second input terminal for applying an input signal; a first differential stage supplied with a first reference current, wherein the first differential stage is formed by PMOS-transistors having gate terminals connected to the input terminals; a second differential stage supplied with a second reference current wherein the second differential stage is formed by NMOS-transistors having gate terminals connected to the input terminals; a switching PMOS-transistor which switches through when the input signal is higher than a predetermined first threshold voltage to divert the first reference current supplied to the first differential stage to a first current mirror circuit which mirrors the first reference current; a switching NMOS-transistor which switches through when the input signal is lower than a predetermined second threshold voltage to divert the second reference current supplied to the second differential stage to a second current mirror circuit which mirrors the second reference current; a third differential stage formed by NMOS-transistors having gate terminals connected to the input terminals; wherein the third differential stage is supplied with the mirrored first reference current and replaces the first differential stage when the input signal is higher than the first threshold voltage; and a fourth differential stage formed by PMOS-transistors having gate terminals connected to the input terminals; wherein the fourth differential stage is supplied with the mirrored second reference current and replaces the second differential stage when the input signal is lower than the second threshold voltage.
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Citations
34 Claims
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1-14. -14. (canceled)
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15. A buffer circuit comprising:
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a differential input configured to receive an input signal;
a first differential stage supplied with a first reference current, the first differential stage comprising PMOS-transistors having gate terminals connected to the differential input;
a second differential stage supplied with a second reference current, the second differential stage comprising NMOS-transistors having gate terminals connected to the differential input;
a switching PMOS-transistor operable to, when the input signal is higher than a predetermined first threshold voltage, divert the first reference current from the first differential stage to a first current mirror circuit configured to mirror the first reference current;
a switching NMOS-transistor operable to, when the input signal is lower than a predetermined second threshold voltage, divert the second reference current from the second differential stage to a second current mirror circuit configured to mirror the second reference current;
a third differential stage comprising NMOS-transistors having gate terminals connected to the differential input, wherein the third differential stage is configured to receive the mirrored first reference current when the input signal is higher than the first threshold voltage; and
a fourth differential stage comprising PMOS-transistors having gate terminals connected to the differential input, wherein the fourth differential stage is configured to receive the mirrored second reference current when the input signal is lower than the second threshold voltage. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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28. A buffer circuit having first, second and third operating states, the buffer circuit comprising:
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a differential input configured to receive an input signal;
a first differential stage supplied with a first reference current, the first differential stage comprising PMOS-transistors having gate terminals connected to the differential input, the first differential stage configured to generate output currents when the buffer circuit is in the first operating state and when the buffer circuit is in the second operating state;
a second differential stage supplied with a second reference current, the second differential stage comprising NMOS-transistors having gate terminals connected to the differential input, the second differential stage configured to generate output currents when the buffer circuit is in the second operating state and when the buffer circuit is in the third operating state;
a third differential stage comprising NMOS-transistors having gate terminals connected to the differential input, wherein the third differential stage is configured to generate output currents when the buffer circuit is in the third operating state; and
a fourth differential stage comprising PMOS-transistors having gate terminals connected to the differential input, wherein the fourth differential stage is configured to generate output currents when the buffer circuit is in the first operating state. - View Dependent Claims (29, 30, 31, 32, 33, 34)
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Specification