High-frequency active inductor

• US 20050083151A1
• Filed: 09/08/2004
• Published: 04/21/2005
• Est. Priority Date: 09/08/2003
• Status: Active Grant

• Current Assignee: Oregon State University (Oregon University System)
• Original Assignee: Oregon State University (Oregon University System)
• Inventors: Schaumann, Rolf, Daasch, W. Robert, Xiao, Haiqiao
• Granted Patent: US 7,042,317 B2
• Time in Patent Office: Days
• US Class Current: 333/215
• CPC Class Codes: H03H 11/486 Simulating inductances using transconductance amplifiers
• CPC Class Codes: H03H 11/50 using gyrators

Abstract

An active inductor circuit implemented in sub-micron CMOS semiconductor technology is usable at gigaHertz frequencies and includes an input node, a non-inverting transconductor circuit comprising a differential pair of NMOS transistors connected to the input node, an inverting transconductor circuit comprising an NMOS transistor connected to an output node of the non-inverting transconductor circuit and connected to the input node in a gyrator feedback configuration. Varactors coupled to the transconductor circuits tune the frequency and Q of the active inductor circuit.

Claims

1. An active inductor circuit implemented in CMOS semiconductor technology and comprising:

an input node;

a non-inverting transconductor circuit connected to the input node;

an inverting transconductor circuit connected to an output node of the non-inverting transconductor circuit and connected to the input node in a feedback configuration; and

wherein the non-inverting transconductor circuit comprises a differential pair of NMOS transistors.

2. An active inductor circuit according to claim 1 wherein the inverting transconductor circuit comprises an NMOS transistor.

3. An active inductor circuit according to claim 1 wherein:

the non-inverting transconductor circuit comprises a differential pair of NMOS transistors; and

the inverting transconductor circuit comprises an NMOS transistor.

4. An active inductor circuit according to claim 3 wherein:

the non-inverting transconductor circuit comprises a differential pair of NMOS transistors having a first gate terminal forming the input node, a second gate terminal connected to a bias source, and a drain terminal forming the said output node, so that the signal path from input node to output node traverses exclusively NMOS devices.

5. An active inductor circuit according to claim 4 wherein the NMOS devices are sub-micron MOSFET devices.

6. An active inductor circuit according to claim 5 wherein the MOSFET devices in the differential pair are approximately the same size.

7. An active inductor circuit according to claim 6 wherein the MOSFET devices in the differential pair have approximately the same biasing.

8. An active inductor circuit according to claim 1 wherein:

the non-inverting transconductor circuit comprises a differential pair of NMOS transistors;

the inverting transconductor circuit comprises a single NMOS transistor; and

the differential pair followed by the single NMOS transistor form the signal path of the active inductor circuit.

9. An active inductor circuit according to claim 8 wherein the differential pair of NMOS transistors and the single NMOS transistor all have W/L sizes of approximately 3/0.2 microns.

10. An active inductor circuit according to claim 8 and further comprising:

a first variable capacitor coupled to the inverting transconductor circuit for tuning the active inductor circuit, the variable capacitor consisting of a PMOS transistor connected in a varactor configuration.

11. An active inductor circuit according to claim 10 and further comprising:

a second variable capacitor coupled to the noninverting transconductor circuit for tuning the active inductor circuit, the second variable capacitor consisting of a second PMOS transistor connected in a varactor configuration.

12. A method of tuning a high-frequency, CMOS implemented active inductor circuit, the method comprising the steps of:

providing an input node and a non-inverting transconductor circuit connected to the input node;

deploying an inverting transconductor circuit connected to an output of the non-inverting transconductor circuit and connected to the input node in a feedback configuration so as to form a gyrator circuit;

providing a first variable capacitor coupled to the inverting transconductor circuit; and

tuning the active inductor circuit by varying a capacitance of the variable capacitor.

13. A method of tuning an active inductor circuit according to claim 12 and including:

implementing the inverting transconductor circuit as an NMOS transistor; and

implementing the variable capacitor as a PMOS transistor;

wherein the PMOS transistor is connected to the gate of the NMOS transistor.

14. A method of tuning an active inductor circuit according to claim 13 wherein said varying the capacitance of the variable capacitor comprises adjusting a bias voltage applied to the substrate of the PMOS transistor.

15. A method of tuning an active inductor circuit according to claim 13 further comprising:

providing a second variable capacitor coupled to the non-inverting transconductor circuit; and

tuning the active inductor circuit by varying a capacitance of the second variable capacitor.

16. A method of tuning a high-frequency, CMOS implemented active inductor circuit, the method comprising the steps of:

providing an input node and a non-inverting transconductor circuit connected to the input node;

providing an inverting transconductor circuit connected to an output of the non-inverting transconductor circuit and connected to the input node in a feedback configuration so as to form a gyrator circuit;

wherein the non-inverting transconductor circuit comprises a differential pair of NMOS transistors;

providing a first variable capacitor coupled to the differential pair of NMOS transistors; and

tuning the active inductor circuit by varying a capacitance of the first variable capacitor.

17. A method of tuning an active inductor circuit according to claim 16 wherein the first variable capacitor is connected to a common source node of the differential pair.

18. A method of tuning an active inductor circuit according to claim 17 including implementing the variable capacitor as a PMOS transistor.

19. A method of tuning an active inductor circuit according to claim 18 wherein said varying the capacitance of the variable capacitor comprises adjusting a bias voltage V_Q applied to the substrate of the PMOS transistor.

20. An active inductor circuit implemented in CMOS semiconductor technology and comprising:

a non-inverting transconductor circuit comprising first and second NMOS transistors arranged in a differential pair configuration;

a gate terminal of the first NMOS transistor defining an input node, and a drain terminal of the second NMOS transistor defining an output node; and

an inverting transconductor circuit comprising a third NMOS transistor connected to the output node of the NMOS differential pair and connected to the input node in a feedback configuration; and

wherein

a signal path from the input node to the output node traverses exclusively NMOS devices.

21. A method of tuning a CMOS active inductor circuit fabricated in accordance with claim 20, the tuning method comprising the steps of:

providing a first bias current to the third NMOS transistor; and

varying the first bias current, thereby adjusting the operating characteristics of the active inductor circuit.

22. A method of tuning a CMOS active inductor circuit according to claim 21 and further comprising:

providing a second bias current to the differential pair of NMOS transistors; and

varying the second bias current, thereby adjusting the operating characteristics of the active inductor circuit.

23. A method of tuning a CMOS active inductor circuit according to claim 21 and further comprising:

adding a first capacitive element to the feedback path between the output node and the third NMOS transistor; and

varying a capacitance of the first capacitive element, thereby adjusting the operating characteristics of the active inductor circuit.

24. A method of tuning a CMOS active inductor circuit according to claim 23 wherein the first capacitive element comprises a varactor.

25. A method of tuning a CMOS active inductor circuit according to claim 23 wherein the first capacitive element consists of a PMOS transistor arranged with its gate connected to the said output node.

26. A method of tuning a CMOS active inductor circuit according to claim 25 wherein said varying the capacitance of the first capacitive element comprises varying a bias voltage applied to a substrate of the PMOS transistor.

27. A method of tuning a CMOS active inductor circuit according to claim 21 and further comprising:

adding a capacitive element to a common source node of the NMOS differential pair; and

varying a capacitance of the capacitive element, thereby adjusting the operating characteristics of the active inductor circuit.

28. A method of tuning a CMOS active inductor circuit according to claim 27 wherein the capacitive element comprises a PMOS transistor arranged to form a varactor.

29. A method of tuning a CMOS active inductor circuit according to claim 28 wherein said varying the capacitance of the capacitive element comprises varying a bias voltage applied to a substrate of the PMOS transistor.

30. A method of tuning a CMOS active inductor circuit according to claim 21 and further comprising:

adding a first capacitive element to the feedback path between the output node and the third NMOS transistor; and

adjusting a capacitance of the first capacitive element, thereby adjusting the operating characteristics of the active inductor circuit;

adding a second capacitive element to a common source node of the NMOS differential pair; and

adjusting a capacitance of the second capacitive element, thereby adjusting the operating characteristics of the active inductor circuit.

31. A method of tuning a CMOS active inductor circuit according to claim 30 wherein both the first and second capacitive elements are PMOS transistors arranged in a varactor configuration.

32. A method of tuning a CMOS active inductor circuit according to claim 21 including tuning the biasing current to the noninverting transconductor, thereby adjusting the operating characteristics of the active inductor circuit (Q).

33. A method of tuning a CMOS active inductor circuit according to claim 21 including tuning the biasing current to the inverting transconductor, thereby adjusting the operating characteristics of the active inductor circuit (f₀).