Method of driving a shift register, a shift register, a liquid crystal display device having the shift register

• US 20050083292A1
• Filed: 12/08/2004
• Published: 04/21/2005
• Est. Priority Date: 06/15/2002
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Back-Won Lee, Seung-Hwan Moon
• Inventors: Moon, Seung-Hwan, Lee, Back-Won
• Granted Patent: US 7,696,974 B2
• Time in Patent Office: Days
• US Class Current: 345/100
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 3/3685 Details of drivers for data electrodes
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

In a shift register and LCD device having the shift register that may be employed in the liquid crystal display device having a large screen size and a large resolution, the shift register includes stages connected with each other and each of the stages have a carry buffer for generating a carry signal. The pull-down transistor of each of the stages of the shift register is divided into a first pull-down transistor and a second pull-down transistor. A power voltage Vona larger than the power voltage Von applied to a clock generator is applied to the shift register. A signal delay due to the RC delay of the gate lines may be minimized, the shift register is independent of the variation of the threshold voltage of the TFTs, and image display quality may not be deteriorated.

Claims

1. A shift register including a plurality of stages, the stages receiving a first clock signal and a second clock signal to sequentially produce a plurality of scan line driving signals for selecting a plurality of scan lines, each of the stages comprising:

a carry buffer configured to provide one of next stages with a carry signal corresponding to the first clock signal or the second clock signal, the second clock signal having a phase different from a phase of the first clock signal;

a pull-up part configured to provide an output terminal with a first scan line driving signal corresponding to the first clock signal or the second clock signal;

a pull-down part configured to provide the output terminal with a first power voltage;

a pull-up driver part configured to turn on the pull-up part in response to the carry signal provided from one of previous stages and configured to turn off the pull-up part in response to a second scan line driving signal of the one of the next stages; and

a pull-down driver part configured to turn off the pull-down part in response to the carry signal provided from the one of the previous stages and configured to turn on the pull-up part in response to the second scan line driving signal of the one of the next stages.

2. The shift register of claim 1, wherein the carry buffer includes a first transistor for receiving the first or the second clock signal through a first drain electrode of the first transistor to output the carry signal in response to an output signal of the pull-down driver part through a first source electrode of the first transistor to one of the next stages, and the output signal is applied to a first gate electrode of the first transistor.

3. The shift register of claim 2, wherein the first transistor is formed at a position adjacent to the pull-up part so as to supply the first or the second clock signal to the pull-up driver part of the one of the next stages.

4. A display device comprising:

a display cell array formed on a substrate, the display cell array including a plurality of gate lines, a plurality of data lines and a plurality of switching elements, the switching elements coupled to the gate lines and the data lines;

a data driver circuit for providing each of the data lines with an image signal; and

a gate driver circuit including a shift register, the shift register including a plurality of stages, the stages receiving a first clock signal and a second clock signal to sequentially produce a plurality of gate line driving signals for selecting the gate lines, each of the stages comprising;

a carry buffer configured to provide one of next stages with a carry signal corresponding to the first clock signal or the second clock signal, the second clock signal having a phase different from a phase of the first clock signal;

a pull-up part configured to provide an output terminal with a first gate line driving signal corresponding to the first clock signal or the second clock signal;

a pull-down part configured to provide the output terminal with a first power voltage;

a pull-up driver part configured to turn on the pull-up part in response to the carry signal provided from one of previous stages and configured to turn off the pull-up part in response to a second gate line driving signal of the one of the next stages; and

a pull-down driver part configured to turn off the pull-down part in response to the carry signal provided from the one of the previous stages and configured to turn on the pull-up part in response to the second gate line driving signal of the one of the next stages.

5. A method of driving a shift register, the shift register including a plurality of stages, the stages receiving a first clock signal and a second clock signal to sequentially produce a plurality of scan line driving signals for selecting a plurality of scan lines, the method comprising:

providing one of next stages with a carry signal corresponding to the first clock signal or the second clock signal, the second clock signal having a phase different from a phase of the first clock signal;

producing a first scan line driving signal corresponding to the first clock signal or the second clock signal in response to the carry signal outputted from one of previous stages; and

lowering a first voltage level of the first scan line driving signal outputted from a present stage in response to a second scan line driving signal outputted from the one of the next stages.

6. A shift register including a plurality of stages, a first stage receiving a scan start signal, the stages receiving a first clock signal and a second clock signal to sequentially produce a plurality of scan line driving signals for selecting a plurality of scan lines, each of the stages comprising:

a first carry buffer configured to provide one of next stages with a first carry signal corresponding to the first clock signal or the second clock signal, the second clock signal having a phase different from a phase of the first clock signal;

a pull-up part configured to provide a first output terminal with a first scan line driving signal corresponding to the first clock signal or the second clock signal;

a pull-down part configured to provide the first output terminal with a first power voltage;

a pull-up driver part configured to turn on the pull-up part in response to a second carry signal outputted from the first carry buffer of one of previous stages and configured to turn off the pull-up part in response to a second scan line driving signal of the one of the next stages;

a pull-down driver part configured to turn off the pull-down part in response to the first carry signal provided from the first carry buffer of the one of the previous stages and configured to turn on the pull-up part in response to the second scan line driving signal of the one of the next stages; and

a second carry buffer configured to lower a first voltage level of the second carry signal, the first carry signal outputted from the first carry buffer of the one of the previous stages to be applied to the pull-up part.

7. A display device comprising:

a display cell array formed on a substrate, the display cell array including a plurality of gate lines, a plurality of data lines and a plurality of switching elements, the switching elements coupled to the gate lines and the data lines;

a data driver circuit configured to provide each of the data lines with an image signal; and

a gate driver circuit including a shift register, the shift register including a plurality of stages, a first stage receiving a scan start signal, the stages receiving a first clock signal and a second clock signal to sequentially produce a plurality of gate line driving signals for selecting a plurality of gate lines, each of the stages comprising;

a first carry buffer configured to provide one of next stages with a first carry signal corresponding to the first clock signal or the second clock signal, the second clock signal having a phase different from a phase of the first clock signal;

a pull-up part configured to provide a first output terminal with a first gate line driving signal corresponding to the first clock signal or the second clock signal;

a pull-down part configured to provide the first output terminal with a first power voltage;

a pull-up driver part configured to turn on the pull-up part in response to a second carry signal outputted from the first carry buffer of one of previous stages and configured to turn off the pull-up part in response to a second gate line driving signal of the one of the next stages;

a pull-down driver part configured to turn off the pull-down part in response to the first carry signal provided from the first carry buffer of the one of the previous stages and configured to turn on the pull-up part in response to the second gate line driving signal of the one of the next stages; and

a second carry buffer configured to lower a first voltage level of the second carry signal, the first carry signal outputted from the first carry buffer of the one of the previous stages to be applied to the pull-up part.

8. A shift register including a plurality of stages, the stages receiving a first clock signal and a second clock signal to sequentially produce a plurality of scan line driving signals for selecting a plurality of scan lines, each of the stages comprising:

a pull-up switching device configured to provide an output terminal of each of the stages with a first scan line driving signal corresponding to the first clock signal or the second clock signal;

a first pull-up driver switching device configured to turn on the pull-up switching device in response to a scan start signal or a second scan line driving signal outputted from one of previous stages;

a second pull-up driver switching device configured to turn off the pull-up switching device in response to a third scan line driving signal outputted from one of next stages;

a first pull-down switching device configured to provide the output terminal with a first power voltage;

a pull-down driver switching device configured to turn off the pull-down switching device in response to the scan start signal or the second scan line driving signal outputted from the one of the previous stages; and

a second pull-down switching device, the second pull-down switching device being turned on in response to the third scan line driving signal to provide the output terminal with the first power voltage.

9. A display device comprising:

a display cell array formed on a substrate, the display cell array including a plurality of gate lines, a plurality of data lines and a plurality of switching elements, the switching elements coupled to the gate lines and the data lines;

a data driver circuit configured to provide each of the data lines with an image signal; and

a gate driver circuit including a shift register, the shift register including a plurality of stages, the stages receiving a first clock signal and a second clock signal to sequentially produce a plurality of gate line driving signals for selecting a plurality of gate lines, each of the stages comprising;

a pull-up switching device configured to provide an output terminal of each of the stages with a first gate line driving signal corresponding to the first clock signal or the second clock signal;

a first pull-up driver switching device configured to turn on the pull-up switching device in response to a scan start signal or a second gate line driving signal outputted from one of previous stages;

a second pull-up driver switching device configured to turn off the pull-up switching device in response to a third gate line driving signal outputted from one of next stages;

a first pull-down switching device configured to provide the output terminal with a first power voltage;

a pull-down driver switching device configured to turn off the pull-down switching device in response to the scan start signal or the second gate line driving signal outputted from the one of the previous stages; and

a second pull-down switching device, the second pull-down switching device being turned on in response to the third gate line driving signal to provide the output terminal with the first power voltage.

10. A shift register including a plurality of stages, the stages receiving a first clock signal and a second clock signal to sequentially produce a plurality of scan line driving signals for selecting a plurality of scan lines, each of the stages comprising:

a first pull-up driver switching device having a first electrode for receiving a second power voltage, a second electrode for receiving a scan start signal or a first scan line driving signal outputted from one of previous stages, and a third electrode coupled to a first node;

a pull-up switching device having a fourth electrode for receiving the first clock signal or the second clock signal, a fifth electrode coupled to the first node, and a sixth electrode coupled to an output terminal;

a first pull-down switching device having a seventh electrode coupled to the output terminal, an eighth electrode coupled to a second node, and a ninth electrode for receiving a first power voltage;

a second pull-down switching device having a tenth electrode coupled to the output terminal, an eleventh electrode for receiving a second gate line driving signal outputted from one of next stages, and a twelfth electrode for receiving the first power voltage;

a capacitor coupled between the first node and the output terminal;

a second pull-up driver switching device having a thirteenth electrode coupled to the first node, a fourteenth electrode for receiving the second gate line driving signal outputted from the one of the next stages, and a fifteenth electrode for receiving the first power voltage;

a third pull-up driver switching device having a sixteenth electrode coupled to the first node, a seventeenth electrode coupled to the second node, and an eighteenth electrode for receiving the first power voltage;

a first pull-up driver switching device having a nineteenth electrode and a twentieth electrode commonly coupled with each other to receive the second power voltage, and a twenty first electrode coupled to the second node; and

a second pull-down driver switching device having a twenty second electrode coupled to the second node, a twenty third electrode coupled to the first node, and a twenty fourth electrode for receiving the first power voltage.