ESD protection circuit between different voltage sources

• US 20050083623A1
• Filed: 10/13/2004
• Published: 04/21/2005
• Est. Priority Date: 10/14/2003
• Status: Active Grant

• Current Assignee: Realtek Semiconductor Corp.
• Original Assignee: Realtek Semiconductor Corp.
• Inventors: Yeh, Ta-Hsun, Lin, Yung-Hao, Jean, Yuh-Sheng
• Granted Patent: US 7,245,467 B2
• Time in Patent Office: Days
• US Class Current: 361/56
• CPC Class Codes: H01L 27/0259 using bipolar transistors as protective elements
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An ESD protection circuit for hybrid voltage sources includes a first bipolar transistor set and a second bipolar transistor set, a first detection circuit, and a second detection circuit. The ON/OFF states of the first bipolar transistor set and the second bipolar transistor set are determined by the first and the second detection circuit, and the ON/OFF states function to isolate terminals of the different voltage sources and discharge electrostatic charges injected into one of the terminals.

Claims

1. An ESD (electrostatic discharge) circuit for protecting a first internal circuit and a second internal circuit from an electrostatic charge, the first internal circuit coupled between two terminals VDD1 and VSS1 and the second internal circuit coupled between two terminals VDD2 and VSS2, the ESD circuit comprising:

a first transistor set comprising at least one transistor coupled between VDD1 and VDD2;

a first detecting circuit coupled between VDD1 and VSS1 for detecting the electrostatic charge, and coupled to the first transistor set; and

a second detecting circuit coupled between VDD2 and VSS2 for detecting the electrostatic charge, and coupled to the first transistor set;

wherein if the first detecting circuit or the second detecting circuit detects the electrostatic charge injected into the VDD1 or the VDD2, the first transistor set is turned on to discharge the electrostatic charge.

2. The ESD circuit of claim 1, wherein the first transistor set comprises:

a first transistor coupled between the VDD1 and the VDD2, and coupled to the first detecting circuit; and

a second transistor coupled between the VDD1 and the VDD2, and coupled to the second detecting circuit;

wherein if the first detecting circuit detects the electrostatic charge injected into the VDD1, the first transistor is turned on to discharge the electrostatic charge, and if the second detecting circuit detects the electrostatic charge injected into the VDD2, the second transistor is turned on to discharge the electrostatic charge.

3. The ESD circuit of claim 1, wherein the electrostatic charge injected into the VDD1 is discharged to the VSS1 through the first detecting circuit, to the VDD2 through the first transistor set, or to the VSS2 through the first transistor set and the second detecting circuit.

4. The ESD circuit of claim 1, wherein the electrostatic charge injected into the VDD2 is discharged to the VSS2 through the second detecting circuit, to the VDD1 through the first transistor set, or to the VSS1 through the first transistor set and the first detecting circuit.

5. The ESD circuit of claim 1, wherein the first transistor set comprises at least a bipolar junction transistor (BJT).

6. The ESD circuit of claim 1, wherein the first transistor set comprises the transistor having:

a first electrode coupled to the VDD1;

a first insulator surrounding the first electrode;

a second electrode surrounding the first insulator and coupled to the first electrode;

a second insulator surrounding the second electrode; and

a third electrode surrounding the second insulator and coupled to the second electrode and the VDD2.

7. The ESD circuit of claim 1 ,.further comprising:

a second transistor set comprising at least one transistor coupled between VSS1 and VSS2;

wherein if the first detecting circuit or the second detecting circuit detects the electrostatic charge injected into the VDD1 or the VDD2, the second transistor set is turned on to discharge the electrostatic charge.

8. The ESD circuit of claim 7, wherein the electrostatic charge injected into the VDD1 is discharged to the VSS2 through the first detecting circuit and the second transistor set.

9. The ESD circuit of claim 7, wherein the electrostatic charge injected into the VDD2 is discharged to the VSS1 through the second detecting circuit and the second transistor set.

10. The ESD circuit of claim 7, wherein the second transistor set comprises:

a third transistor coupled between the VSS1 and the VSS2, and coupled to the first detecting circuit; and

a fourth transistor coupled between the VSS1 and the VSS2, and coupled to the second detecting circuit;

wherein if the first detecting circuit detects the electrostatic charge injected into the VDD1, the third transistor is turned on to discharge the electrostatic charge, and if the second detecting circuit detects the electrostatic charge injected into the VDD2, the fourth transistor is turned on to discharge the electrostatic charge.

11. The ESD circuit of claim 7, wherein the second transistor set comprises at least a bipolar junction transistor (BJT).

12. The ESD circuit of claim 7, wherein the second transistor set comprises the transistor having:

a first electrode coupled to the VSS1;

a first insulator surrounding the first electrode;

a second electrode surrounding the first insulator and coupled to the first electrode;

a second insulator surrounding the second electrode; and

a third electrode surrounding the second insulator and coupled to the second electrode and the VSS2.

13. The ESD circuit of claim 1, wherein at least one of the first detecting circuit and second detecting circuit comprises:

a detector coupled to the first transistor set and turning on the first transistor set during the occurrence of the electrostatic charge; and

a discharging circuit coupled to the detector for discharging the electrostatic charge.

14. The ESD circuit of claim 1, further comprising at least one first diode coupled between the VDD1 and VSS1, wherein the electrostatic charge injected into the VSS1 may be discharged through the first diode.

15. The ESD circuit of claim 1, further comprising at least one second diode coupled between the VDD2 and VSS2, wherein the electrostatic charge injected into the VSS2 may be discharged through the second diode.

16. An ESD (Electrostatic Discharging) protection method for protecting a first internal circuit and a second internal circuit from an electrostatic charge, the first internal circuit coupled between two terminals VDD1 and VSS1 and the second internal circuit coupled between two terminals VDD2 and VSS2, the method comprising the following steps:

disposing a first transistor set comprising at least one transistor coupled between the VDD1 and the VDD2;

using a first detecting circuit and a second detecting circuit for detecting the electrostatic charge, wherein the first detecting circuit is coupled between the VDD1 and the VSS1, and the second detecting circuit is coupled between the VDD2 and the VSS2;

when the first detecting circuit or the second detecting circuit detects the electrostatic charge injected into the VDD1 or the VDD2, turning on the first transistor set to discharge the electrostatic charge.

17. The ESD protection method of claim 16, wherein the first transistor set comprises:

a first transistor coupled between the VDD1 and the VDD2, and coupled to the first detecting circuit; and

a second transistor coupled between the VDD1 and the VDD2, and coupled to the second detecting circuit;

wherein if the first detecting circuit detects the electrostatic charge injected into the VDD1, the first transistor is turned on to discharge the electrostatic charge, and if the second detecting circuit detects the electrostatic charge injected into the VDD2, the second transistor is turned on to discharge the electrostatic charge.

18. The ESD protection method of claim 16, wherein the first transistor set comprises at least a bipolar junction transistor (BJT) comprising:

a first electrode coupled to the VDD1;

a first insulator surrounding the first electrode;

a second electrode surrounding the first insulator and coupled to the first electrode;

a second insulator surrounding the second electrode; and

a third electrode surrounding the second insulator and coupled to the second electrode and the VDD2.

19. The ESD protection method of claim 16, further comprising:

disposing a second transistor set comprising at least one transistor coupled between VSS1 and VSS2; and

when the first detecting circuit or the second detecting circuit detects the electrostatic charge injected into the VDD1 or the VDD2, turning on the second transistor set to discharge the electrostatic charge.

20. A method for forming a bipolar transistor having a collector and an emitter respectively coupled to a first power source terminal and a second power source terminal, wherein the bipolar transistor is for providing a path for discharging an electrostatic current and for isolating the first power source terminal from the second power source terminal during the absence of the electrostatic current, the method comprising the steps of:

forming a deep N-well on a top surface of a substrate;

forming a P-well at a central region of the deep N-well;

forming an N-well surrounding the P-well;

forming a first isolation structure and a second isolation structure in the P-well, both of the first isolation structure and the second isolation structure are ring-shaped and separated from each other;

forming a N plus region inside the region surrounded by the first isolation structure, and outside the region surrounded by the second isolation structure; and

forming a P plus region between the first isolation structure and the second isolation structure.