Granularity memory column access

• US 20050083721A1
• Filed: 10/22/2004
• Published: 04/21/2005
• Est. Priority Date: 09/07/2001
• Status: Abandoned Application

• Current Assignee: Craig E. Hampel, Frederick A. Ware, Richard E. Warmke
• Original Assignee: Craig E. Hampel, Frederick A. Ware, Richard E. Warmke
• Inventors: Hampel, Craig E., Ware, Frederick A., Warmke, Richard E.
• Application Number:
  US10/970,947
• Publication Number:
  US 20050083721A1
• Time in Patent Office: Days
• US Class Current: 365/145
• CPC Class Codes: G09G 2360/122 Tiling
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

A memory device includes multiple data I/O lanes and corresponding lane or column decoders. Instead of providing the same address to each column decoder, decoder logic calculates potentially different column addresses depending on the needs of the device utilizing the memory. For example, the column addresses might be based on a received CAS address and an accompanying offset. This allows data access at alignments that do not necessarily correspond to CAS alignments. The technique is utilized in conjunction with graphics systems in which tiling is used. In systems such as this, memory offsets are specified in terms of pixel columns and rows. The technique is also used in conjunction with a router such as a TCP/IP router, in which individual packets are aligned at CAS boundaries. In this situation, the decoder logic is alternatively configurable to allow access of either an information packet or a plurality of packet headers during a single memory access cycle.

Claims

1-2. -2. (canceled)

3. An integrated circuit memory device comprising:

first and second memory arrays;

a first column decoder, coupled to the first memory array, to select first data in response to a first column address received during a column operation; and

a second column decoder, coupled to the second memory array, to select second data in response to a second column access received during the column operation.

4. The integrated circuit memory device of claim 3, further comprising a row decoder circuit to enable, based on a row address, a first row of data to be output from the first memory array and a second row of data to be output from the second memory array, wherein the first data is selected by the first column decoder from the first row of data and the second data is selected by the second column decoder from the second row of data.

5. The integrated circuit memory device of claim 4, further comprising:

first sense amplifiers to store the first row of data output from the first memory array; and

second sense amplifiers to store the second row of data output from the second memory array.

6. The integrated circuit memory device of claim 5 further comprising:

a first plurality of internal signal lines coupled to the first sense amplifiers to enable the first data selected by the first column decoder to be output from the integrated circuit memory device during the column operation; and

a second plurality of internal signal lines coupled to the second sense amplifiers to enable the second data selected by the second column decoder to be output from the integrated circuit memory device during the column operation.

7. The integrated circuit memory device of claim 3, wherein the second column address is different than the first column address.

8. The integrated circuit memory device of claim 3, further comprising address specification logic coupled to the first column decoder and the second column decoder, the address specification logic to receive a third column address and a first adjustment value and generate the first column address based, at least in part, on the first adjustment value and the third column address.

9. The integrated circuit memory device of claim 8, wherein the address specification logic is to receive a second adjustment value and generate the second column address based, at least in part, on the second adjustment value and the third column address.

10. The integrated circuit memory device of claim 8, further comprising a register to store the first adjustment value.

11. The integrated circuit memory device of claim 10, wherein the memory device stores the first adjustment value in the register in response to a command.

12. The integrated circuit memory device of claim 3, wherein:

the first column decoder derives the first column address at least in part from a third column address and a first offset; and

the second column decoder derives the second column address at least in part from the third column address and a second offset.

13. A graphics system comprising:

a dynamic random access memory device including;

a first memory array having storage cells and a second memory array having storage cells;

a first column decoder coupled to the first memory array, the first column decoder to access first data from a column of storage units in the first memory array based on a first column address; and

a second column decoder coupled to the second memory array, the second column decoder to access second data from a column of storage units in the second memory array based on a second column address; and

a graphics controller, coupled to the dynamic random access memory device, to access in parallel, the first data from the column of storage units in the first memory array, and the second data from the column of storage units in the second memory array.

14. The graphics system of claim 13, wherein the graphics controller is coupled to the dynamic random access memory to access in parallel during a column access cycle, both the first data from the column of storage units in the first memory array, and the second data from the column of storage units in the second memory array.

15. The graphics system of claim 13, wherein the dynamic random access memory device further includes a first data lane coupled to the first column decoder and a second data lane coupled to the second column decoder, wherein the graphics controller is to access the column of storage units in the first memory array through the first data lane and the memory controller is to access the column of storage units in the second memory array through the second data lane.

16. The graphics system of claim 15, wherein the first data lane is a byte in width and the second data lane is a byte in width.

17. The graphics system of claim 13 wherein the dynamic random access memory device further includes a row decoder circuit to select, based on a row address, a first row in the first memory array and a second row in the second memory array, wherein the column of storage units in the first memory array is located in the first row and the column of storage units in the second memory array is located in the second row.

18. The graphics system of claim 13, wherein the second column address is different than the first column address.

19. The graphics system of claim 13, further comprising address specification logic coupled to the first column decoder and the second column decoder, the address specification logic to generate the first column address using the first adjustment value and a third column address.

20. The graphics system of claim 13, wherein the dynamic random access memory device comprises a register to store the first adjustment value in response to a command from the graphics controller.

21. The graphics system of claim 13, wherein:

the first column decoder derives the first column address using a third column address and a first offset; and

the second column decoder derives the second column address using the third column address and a second offset.

22. A method of operation in a system having a memory device and a controller device coupled to one another, wherein the memory device includes a first memory array and a second memory array, the method comprising:

selecting a column of storage units in the first memory array based on a first column address;

selecting a column of storage units in the second memory array based on a second column address; and

the controller device accessing, in parallel, data from the column of storage units in the first memory array and data from the column of storage units in the second memory array.

23. The method of claim 22, further comprising selecting, based on a row address, a first row in the first memory array and a second row in the second memory array, wherein the column of storage units in the first memory array is located in the first row and the column of storage units in the second memory array is located in the second row.

24. The method of claim 22, faker comprising:

the memory device receiving a third column address from the controller device;

the memory device receiving a first adjustment value from the controller device; and

the memory device generating the first column address using the first adjustment value and the third column address.

25. The method of claim 24, further comprising:

the memory device receiving a second adjustment value from the controller device; and

the memory device generating the second column address using the second adjustment value and the third column address.

26. The method of claim 24, further comprising:

the memory device receiving a command from the controller device; and

the memory device storing the first adjustment value in the register in response to the command.

27. The method of claim 22, further comprising:

the controller device providing, to the memory device, a third column address, a first offset and a second offset;

the memory device deriving the first column address using the third column address and the first offset; and

the memory device deriving the second column address using the third column address and the second offset.

28. The method of claim 22, wherein selecting the column of storage units in the first memory array based on the first column address is performed concurrently with selecting the column of storage units in the second memory array based on the second column address.

29. A memory device comprising:

a first memory array having storage units and a second memory array having storage units;

a first column decoder coupled to the first memory array, the first column decoder to select during a column operation, a column of storage units in the first memory array based on a first column address; and

a second column decoder coupled to the second memory array, the second column decoder to select, during the column operation, a column of storage units in the second memory array based on a second column address,

a row decoder circuit to select, based on a row address, a first row in the first memory array and a second row in the second memory array, wherein the column of storage units in the first memory array is located in the first row and the column of storage units in the second memory array is located in the second row;

first sense amplifiers, coupled to the first memory array, to sense data stored in the first row;

second sense amplifiers, coupled to the second memory array, to sense data stored in the second row;

a first plurality of internal lines to transfer first data corresponding to the column of storage units in the first memory array with the first sense amplifiers during the column operation;

a second plurality of internal lines to transfer second data corresponding to the column of storage units in the second memory array with the second sense amplifiers during the column operation; and

an external interface to provide access to the first data and the second data during the column operation.