Programmable logic device for wireless local area network

• US 20050084076A1
• Filed: 12/03/2001
• Published: 04/21/2005
• Est. Priority Date: 12/03/2001
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Rangasayee, Krishna, Dhir, Amit
• Granted Patent: US 7,142,557 B2
• Time in Patent Office: Days
• US Class Current: 379/55.100
• CPC Class Codes: H04L 12/5692 Selection among different networks
• CPC Class Codes: H04L 69/18 Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

Method and apparatus for a wireless local area network programmable logic device is described. More particularly, a field programmable gate array (FPGA) is coupled to memory having programming instructions for configuring the FPGA with a medium access layer selected from more than one type of medium access layers. A physical layer is hardwired or embedded on the FPGA, or a separate integrated circuit for the physical layer is used. Additionally, the memory comprises programming instructions for a baseband controller, and may include programming instructions for a baseband processor, for configuring the FPGA in accordance therewith. In this manner, a single physical layer may be used with an FPGA to provide a multi-platform application specific standard product (ASSP). This is especially advantageous for providing multi-platform devices for use in countries or applications where one or more standards may be employed.

Claims

1. A subsystem for use in a wireless local area networking device, comprising:

a transceiver;

programmable gates coupled to the transceiver; and

memory coupled to the programmable gates, the memory storing instructions for programming a first portion of the programmable gates as a selected one of a first type of a medium access layer and a second type of a medium access layer, the first type of the medium access layer different from the second type of the medium access layer, wherein the first type of the medium access layer and the second type of the medium access layer are compatible with the transceiver, the memory storing instructions for programming a second portion of the programmable gates as a baseband controller.

2. The subsystem of claim 1 wherein the transceiver is coupled to the programmable gates through programmable input/output blocks.

3. The subsystem of claim 1 wherein the first type of medium access control layer comprises a Carrier Sense Multiple Access protocol, and the second type of medium access control layer comprises a Time Division Multiple Access protocol.

4. The subsystem of claim 1 wherein the transceiver and the programmable gates are formed as an integrated circuit.

5. The subsystem of claim 4 wherein the integrated circuit is a Field Programmable Gate Array.

6. The subsystem of claim 1 wherein the memory stores instructions for programming a third portion of the programmable gates as a baseband processor.

7. A subsystem for use in a wireless local area network device, comprising:

a transceiver;

programmable gates coupled to the transceiver; and

memory coupled to the programmable gates, the memory storing instructions for programming a first portion of the programmable gates with a selected one of a first data-link layer and a second data-link layer, the first data-link layer different from the second data-link layer, wherein the first data-link layer and the second data-link layer are compatible with the transceiver, the memory storing instruction for programming a second portion of the programmable gates with a baseband controller.

8. The subsystem of claim 7 further comprising a baseband processor coupled to the programmable gates.

9. The subsystem of claim 8 wherein the transceiver and the baseband processor are coupled to the programmable gates through programmable input/output blocks.

10. The subsystem of claim 9 wherein the first data-link layer comprises a first logical link control sub-layer and a first medium access control sub-layer, and the second data-link layer comprises a second logical link control sub-layer and a second medium access control sub-layer.

11. The subsystem of claim 10 wherein the first medium access control sub-layer comprises a Carrier Sense Multiple Access protocol, and the second medium access control sub-layer comprises a Time Division Multiple Access protocol.

12. A circuit board, comprising:

a field programmable gate array comprising programmable configuration logic blocks and programmable input/output blocks coupled to the programmable configuration logic blocks;

a radio coupled to the programmable configuration logic blocks through the programmable input/output blocks;

program memory coupled to the programmable configuration logic blocks through the programmable input/output blocks;

data memory coupled to the programmable configuration logic blocks through the programmable input/output blocks; and

an interface transceiver coupled to the programmable configuration logic blocks through the programmable input/output blocks;

the program memory comprising programming instructions for the programmable configuration logic blocks to be configured as,

a radio interface and controller;

a medium access control protocol engine and configuration controller; and

a baseband processor interface.

13. The circuit board of claim 12 wherein the program memory comprises programming instruction for the programmable configuration logic blocks to be configured as a baseband processor.

14. The circuit board of claim 12 wherein the program memory comprises programming instruction for the programmable configuration logic blocks to be configured as an encryption engine.

15. The circuit board of claim 12 wherein the program memory comprises programming instruction for the programmable configuration logic blocks to be configured as a memory controller and host bus interface.

16. The circuit board of claim 12 wherein the program memory comprises programming instruction for the programmable configuration logic blocks to be configured as a memory controller, host device interface and host device controller.

17. The circuit board of claim 16 wherein the host device interface and the host device controller are user selectable.

18. A method for providing a multi-platform wireless local area network, comprising:

providing a radio;

providing a programmable input/output blocks coupled to the radio;

providing configuration logic blocks coupled to the programmable input/output blocks;

storing a plurality of medium access control layers compatible with the radio and configured to program the configuration logic blocks; and

selectably programming a first portion of the configuration logic blocks with a medium access control layer from the plurality of medium access control layers.

19. The method of claim 18 further comprising:

storing a plurality of encryption algorithms configured to program the configuration logic blocks; and

selectably programming a second portion of the configuration logic blocks with an encryption algorithm from the plurality of encryption algorithms.

20. The method of claim 19 further comprising:

storing a plurality of host interfaces configured to program the configuration logic blocks; and

selectably programming a third portion of the configuration logic blocks with a host interface from the plurality of host interfaces.

21. A circuit board, comprising:

transceiver means for receiving and transmitting information; and

configurable logic means coupled to the transceiver means for communicating therewith, the configurable logic means for programming as a medium access control layer selected from a plurality of medium access control layers.

22. The circuit board of claim 21 further comprising storage means for storing programming means, the programming means for providing configuration instructions for the plurality of medium access control layers for programming a portion of the configurable logic means.

23. The circuit board of claim 22 wherein the storage means are for storing encryption means, the encryption means for providing configuration instruction for configuring another portion of the configurable logic means with an encryption engine.

24. The circuit board of claim 22 wherein the storage means are for storing host interface means, the host interface means for providing configuration instruction for configuring another portion of the configurable logic means with a host interface.