Technique for evaluating a fabrication of a die and wafer

• US 20050085032A1
• Filed: 08/25/2004
• Published: 04/21/2005
• Est. Priority Date: 08/25/2003
• Status: Active Grant

• Current Assignee: Tau-Metrix, Inc.
• Original Assignee: Tau-Metrix, Inc.
• Inventors: Pakdaman, Nader, Aghababazadeh, Majid, Steinbrueck, Gary L., Vickers, James S., Estabil, Jose J.
• Granted Patent: US 7,220,990 B2
• Time in Patent Office: Days
• US Class Current: 438/232
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: G01R 31/31707 Test strategies methods for generation of test sequences G01R31/318371
• CPC Class Codes: G01R 31/31718 Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis mechanical aspects G01R31/2808, G01R31/2851
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

Claims

1. A test structure for evaluating a fabrication of a wafer, the test structure comprising:

a combination of device and interconnect elements that are provided on an active region of a die on the wafer prior to the fabrication of the wafer being completed, wherein the combination can be activated to cause electrical activity that is detectable without affecting a usability of the die or wafer and

wherein the combination of device and interconnect elements is configured so that the electrical activity (i) emphasizes a first fabrication step in the fabrication sequence over another step in the fabrication sequence, and (ii) indicates a value or variation of an attribute or result of the first fabrication step on at least a segment of the die.

2. The test structure of claim 1, wherein the attribute or result of the first fabrication step corresponds to a physical property that is present within the active region of the die.

3. The test structure of claim 1, wherein the attribute or result of the first fabrication step corresponds to an electrical property that is present within the active region of the die.

4. The test structure of claim 1, wherein the combination of device and interconnect elements are configured to emphasize the attribute or result of the first fabrication step over an attribute or result of any other step in the fabrication.

5. The test structure of claim 1, wherein the combination of device and interconnect elements are configured to be indicative of only the first fabrication step.

6. The test structure of claim 1, wherein the electrical activity corresponds to one or more of (i) an output signal, (ii) photon emission, (iii) electron emissions, and (iv) an electrical effect.

7. The test structure of claim 1, wherein the test structure can be at least partially activated by an energy beam, and wherein the electrical activity includes photons produced from a switch element in the combination of device and interconnect elements.

8. The test structure of claim 1, wherein the test structure can be at least partially activated by an energy beam, and wherein the electrical activity includes at least one of an electrostatic, electromagnetic, and inductive signal.

9. The test structure of claim 8, wherein the electrical activity has a characteristic that identifies the test structure from at least some of the other test structures on the die.

10. The test structure of claim 1, wherein the combination of device and interconnect elements includes a plurality of interconnected inverter

11. The test structure of claim 10, wherein the combination of device and interconnect elements includes one or more CMOS inverters.

12. The test structure of claim 1, wherein the combination of device and interconnect elements includes a plurality of transistors, and wherein the combination is configured to exaggerate the influence of transistor gate lengths to transistor gate widths and other electrical parameters for the plurality of transistors.

13. The test structure of claim 1, wherein the combination of device and interconnect elements includes a plurality of transistors, and wherein the combination is configured to exaggerate the influence of transistor gate widths to transistor gate lengths and other electrical parameters for the plurality of transistors

14. The test structure of claim 1, wherein the combination of device and interconnect elements includes a plurality of transistors and an interconnect device, and wherein the combination is configured to exaggerate an influence of interconnect resistance amongst the plurality of transistors and the interconnect device.

15. The test structure of claim 1, wherein the combination of device and interconnect elements includes a plurality of transistors and an interconnect device, and wherein the combination is configured to exaggerate an influence of interconnect capacitance amongst the plurality of transistors and interconnect device.

16. The test structure of claim 1, wherein the combination of device and interconnect elements includes a plurality of transistors and an interconnect device, and wherein the combination is configured to exaggerate an influence of gate capacitance amongst the plurality of transistors and interconnect device.

17. The test structure of claim 16, wherein the combination of device and interconnect elements includes a plurality of transistors and an interconnect device, and wherein the combination is configured to exaggerate an influence of gate film stack on one or more gates of the plurality of transistors.

18. The test structure of claim 16, wherein the combination of device and interconnect elements includes a plurality of transistors and an interconnect device, and wherein the combination is configured to exaggerate an influence of a photoresist step and an etch step in the fabrication sequence.

19. The test structure of claim 16, wherein the combination of device and interconnect elements includes a plurality of transistors and an interconnect device, and wherein the combination is configured to exaggerate an influence of a gate source drain extension implant.

20. The test structure of claim 1, wherein the combination of device and interconnect elements includes a plurality of transistors and an interconnect device, and wherein the combination is configured to exaggerate an influence of contact resistance amongst the plurality of transistors and the interconnect device.

21. The test structure of claim 1, wherein the combination of device and interconnect elements are distributed on one or more of a plurality of die, partial die, and a scribe region of the wafer, and wherein the combination of device and interconnect elements can be activated to cause electrical activity that emphasizes one or more fabrication steps over other fabrication steps in the fabrication of the wafer.

22. The test structure of claim 1, wherein the combination of device and interconnect elements can be activated by a stimulating signal.

23. The test structure of claim 1, wherein the combination of device and interconnect elements can be activated by a modulating signal.

24. A mechanism for evaluating a fabrication of a wafer that includes one or more die, the mechanism comprising:

a plurality of test structures disposed on at least some of the one or more die, wherein the plurality of test structures are segmented into a plurality of classes, and wherein each class of test structures includes;

a combination of device and interconnect elements that are provided on the die prior to the fabrication being completed, wherein the combination can be activated to cause an electrical activity that is detectable without affecting a usability of a chip formed from the die after fabrication is completed;

wherein each combination is configured so that (i) the electrical activity of that combination identifies a value that indicates an attribute or result of one or more steps in the fabrication, and (ii) the electrical activity of that combination is not indicative of an attribute or result of at least a second step in the fabrication;

wherein the wafer includes a class of the test structures for each fabrication step in the set of designated fabrication steps;

wherein the value of each fabrication step in the class of test structures can be used, either individually or in combination with the value of another fabrication step or steps from another class of test structures, to determine information on a result of a particular fabrication step.

25. The mechanism of claim 24, wherein the plurality of test structures may be triggered concurrently.

26. The mechanism of claim 25, wherein the electrical activity from at least some of the plurality of test structures identify those test structures from other test structures on the wafer.

27. The mechanism of claim 26, wherein the electrical activity from at least some of the plurality of test structures are detectable using a common detection apparatus that scans at least some of the wafer without making contact.

28. The mechanism of claim 24, wherein the fabrication step that is indicated by the electrical activity of one or more of the plurality of test structures that corresponds to a physical property that is present within the chip.

29. The mechanism of claim 24, wherein the fabrication step that is indicated by the electrical activity of one or more of the plurality of test structures corresponds to an electrical property that is present within the chip.

30. The mechanism of claim 24, wherein each of the plurality of test structures are at least partially tiggerable by a common energy beam.

31. The mechanism of claim 30, wherein the electrical activity of one or more of the plurality of test structures includes photons produced from a switch element in the combination of device and interconnect elements of the one or more test structures.

32. The mechanism of claim 24, wherein the electrical activity of one or more of the plurality of test structures includes at least one of an electrostatic, electromagnetic, or inductive signal that is created by an output of each of the one or more test structures in response to being triggered.

33. The mechanism of claim 32, wherein the radio-frequency signal of each of the one or more test structures has a characteristic that identifies the test structure from other test structures on the chip.

34. The mechanism of claim 24, wherein the electrical activity of the plurality of test structures are detectable without contact being made to the chip.

35. The mechanism of claim 24, wherein the combination of one or more test structures includes a plurality of interconnected inverters.

36. The mechanism of claim 35, wherein the combination the one or more test structures includes one or more CMOS inverters.

37. The mechanism of claim 24, wherein the combination of one or more of the plurality of test structures includes a plurality of transistors, and wherein each combination of the one or more test structures is configured to minimize a relationship of transistor gate lengths to transistor gate widths for the plurality of transistors.

38. The mechanism of claim 24, wherein the combination of device and interconnect elements includes a plurality of transistors, and wherein the combination is configured to exaggerate the influence of transistor gate widths to transistor gate lengths and other electrical parameters for the plurality of transistors.

39. The mechanism of claim 24, wherein the combination of device and interconnect elements includes a plurality of transistors and an interconnect device, wherein the combination is configured to exaggerate the influence of Interconnect Resistance.

40. The mechanism of claim 24, wherein the combination of device and interconnect elements includes a plurality of transistors and an interconnect device, wherein the combination is configured to exaggerate the influence of Interconnect Capacitance.

41. The mechanism of claim 24, wherein the combination of device and interconnect elements includes a plurality of transistors and an interconnect device, wherein the combination is configured to exaggerate the influence of Gate Capacitance.

42. The mechanism of claim 41, wherein the combination of device and interconnect elements includes a plurality of transistors and an interconnect device, wherein the combination is configured to exaggerate the influence of Gate Film stack on Gate.

43. The mechanism of claim 41, wherein the combination of device and interconnect elements includes a plurality of transistors and an interconnect device, wherein the combination is configured to exaggerate the influence of Gate Photo and Etch.

44. The mechanism of claim 41, wherein the combination of device and interconnect elements includes a plurality of transistors and an interconnect device, wherein the combination is configured to exaggerate the influence of Gate Source Drain Extension implant.

45. The mechanism of claim 24, wherein the combination of device and interconnect elements includes a plurality of transistors and an interconnect device, wherein the combination is configured to exaggerate the influence of Contact Resistance.

46. The mechanism of claim 24, wherein the combination of device and interconnect elements includes a plurality of transistors and an interconnect device, wherein the combination is configured to exaggerate the influence of Contact Resistance.