Method for fabricating NROM memory cells with trench transistors

• US 20050085037A1
• Filed: 12/07/2004
• Published: 04/21/2005
• Est. Priority Date: 06/07/2002
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Willer, Josef, Kleint, Christoph, Deppe, Joachim, Ludwig, Christoph
• Granted Patent: US 7,205,195 B2
• Time in Patent Office: Days
• US Class Current: 438/253
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An electrically conductive bit line layer is applied and patterned into portions arranged parallel to one another before the trench is etched into the semiconductor material, in which case, after the patterning of the bit line layer (3, 4) and before the etching of the trench, an implantation is introduced for the purpose of defining the position of the junctions, or, after the implantation of the n⁺-type well (19) for the source/drain regions, the bit line layer (3, 4) is patterned using an etching stop layer (2) arranged on the semiconductor body (1).

Claims

1. A method of forming a semiconductor device, the method comprising:

providing a semiconductor body that is doped to a first conductivity type;

doping an upper portion of the semiconductor body to a second conductivity type;

forming conductive lines over the semiconductor body;

etching a recess in the semiconductor body between the conductive lines, the recess extending through the upper portion of the semiconductor body;

forming a storage layer in the recess; and

forming a conductor over the storage layer and within the recess.

2. The method of claim 1 wherein providing a semiconductor body comprises providing a semiconductor substrate.

3. The method of claim 1 wherein forming conductive lines comprises forming a conductive layer and etching the conductive layer into conductive lines.

4. The method of claim 3 wherein forming a conductive layer comprises forming a polysilicon layer and forming a metal layer over the polysilicon layer.

5. The method of claim 3 and further comprising forming an etch stop layer prior to forming the conductive layer.

6. The method of claim 5 and further comprising patterning and etching the etch stop layer prior to forming the conductive lines such that remaining portions of the etch stop layer remain over the semiconductor body and spaced from the conductive lines.

7. The method of claim 5 wherein forming the recess comprises etching the etch stop layer.

8. The method of claim 7 and further comprising forming spacers along sidewalls of the conductive lines prior to etching the etch stop layer and wherein etching the recess comprises etching the recess in alignment with the spacers.

9. The method of claim 3 wherein etching the conductive layer further comprises etching into the upper portion of the semiconductor body.

10. The method of claim 1 and further comprising forming spacers along sidewalls of the conductive lines prior to forming the recess.

11. The method of claim 10 wherein forming spacers comprises:

forming an oxide liner over the sidewalls;

forming a nitride layer over the oxide liner; and

anisotropically etching the nitride layer.

12. The method of claim 10 wherein etching the recess comprises etching the recess in alignment with the spacers.

13. The method of claim 1 wherein forming conductive lines comprises forming conductive lines that are in electrical contact with the upper portion of the semiconductor body.

14. The method of claim 1 wherein forming a storage layer comprises forming an oxide-nitride-oxide layer sequence.

15. The method of claim 1 wherein forming a conductor over the storage layer comprises depositing polysilicon in the recess.

16. The method of claim 1 wherein doping the upper portion of the semiconductor body is performed prior to forming the conductive lines.

17. A method for fabricating a semiconductor device that includes a plurality of NROM memory cells, the semiconductor device comprising:

a gate electrode, which is arranged at a top side of a semiconductor body or a semiconductor layer and is isolated from the semiconductor material by dielectric material; and

a source region and a drain region, which are formed in the semiconductor material;

the gate electrode being arranged in a trench formed in the semiconductor material between the source region and the drain region; and

a storage layer being present at least between the source region and the gate electrode and between the drain region and the gate electrode, which storage layer is provided for trapping charge carriers;

the method comprising;

applying at least one electrically conductive bit line layer over the semiconductor body or semiconductor layer;

patterning the at least one electrically conductive bit line layer into portions that are arranged parallel to one another;

etching the trench into the semiconductor material from a top side of the semiconductor layer between said portions; and

after patterning the at least one electrically conductive bit line layer and before the etching of the trench, introducing an implantation to define a position at which a boundary between a source/drain region and a channel region provided at a lower portion of the trench adjoins the trench.

18. The method as claimed in claim 17, wherein the at least one electrically conductive bit line layer comprises at least one material selected from the group consisting of doped polysilicon, tungsten, tungsten silicide, cobalt, cobalt silicide, titanium and titanium silicide.

19. The method as claimed in claim 17, and further comprising:

applying an etching stop layer over the whole area, wherein the at least one electrically conductive bit line layer is applied on said etching stop layer;

after the patterning of the bit line layer and before the etching of the trench, removing the etching stop layer to an extent such that a region free of the material of the etching stop layer is present between the bit line layer and the semiconductor material present underneath; and

filling said region with a contact layer made of an electrically conductive material.

20. The method as claimed in claim 17, wherein, before the etching of the trench, portions of the patterned bit line layer are covered with spacers on both sides and the trench is etched in the region between said spacers.

21. The method as claimed in claim 17, wherein after the etching of the trench the method further comprises:

applying an ONO storage layer; and

introducing a material for the gate electrode into the trench.

22. A method for fabricating a semiconductor device that includes a plurality of NROM memory cells, the semiconductor device comprising:

a gate electrode, which is arranged at a top side of a semiconductor body or a semiconductor layer and is isolated from the semiconductor material by dielectric material; and

a source region and a drain region, which are formed in the semiconductor material;

the gate electrode being arranged in a trench formed in the semiconductor material between the source region and the drain region; and

a storage layer being present at least between the source region and the gate electrode and between the drain region and the gate electrode, which storage layer is provided for trapping charge carriers;

the method comprising;

implanting source/drain regions in the semiconductor body;

applying an etch stop layer over the semiconductor body;

applying at least one electrically conductive bit line layer over the semiconductor body;

patterning the at least one electrically conductive bit line layer into portions that are arranged parallel to one another, the at least one electrically conductive bit line layer using the etch stop layer after implanting the source/drain regions; and

etching the trench into the semiconductor material from a top side of the semiconductor layer between said portions.

23. The method as claimed in claim 22, wherein the at least one electrically conductive bit line layer comprises at least one material selected from the group consisting of doped polysilicon, tungsten, tungsten silicide, cobalt, cobalt silicide, titanium and titanium silicide.

24. The method as claimed in claim 22:

wherein the etch stop layer is applied over the whole area, wherein the at least one electrically conductive bit line layer is applied on said etch stop layer;

after the patterning of the bit line layer and before the etching of the trench, removing the etch stop layer to an extent such that a region free of the material of the etch stop layer is present between the bit line layer and the semiconductor material present underneath; and

filling said region with a contact layer made of an electrically conductive material.

25. The method as claimed in claim 22, wherein, before the etching of the trench, portions of the patterned bit line layer are covered with spacers on both sides and the trench is etched in the region between said spacers.

26. The method as claimed in claim 22, wherein after the etching of the trench the method further comprises:

applying an ONO storage layer; and

introducing a material for the gate electrode into the trench.