Process integration of SOI FETs with active layer spacer

• US 20050085081A1
• Filed: 10/16/2003
• Published: 04/21/2005
• Est. Priority Date: 10/16/2003
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liaw, Jhon Jhy
• Granted Patent: US 7,119,023 B2
• Time in Patent Office: Days
• US Class Current: 438/704
• CPC Class Codes: H01L 21/02046 Dry cleaning only H01L21/02085 takes precedence
• CPC Class Codes: H01L 21/02052 Wet cleaning only H01L21/02085 takes precedence
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/78687 with a multilayer structure or superlattice structure

Abstract

A method of manufacturing a microelectronics device including providing a substrate having an active layer, a dielectric layer and a structural layer, wherein the active layer is formed over the dielectric layer and the dielectric layer is formed over the structural layer. The method further includes forming an opening through the active layer thereby exposing a surface of the dielectric layer and defining active layer sidewalls. A spacer is formed covering a first portion of the exposed dielectric layer surface and substantially spanning one of the active layer sidewalls. At least a second portion of the exposed dielectric layer surface is then cleaned.

Claims

1. A method of manufacturing a microelectronics device, comprising:

providing a substrate having an active layer, a dielectric layer and a structural layer, wherein the active layer is formed over the dielectric layer and the dielectric layer is formed over the structural layer;

forming an opening through the active layer thereby exposing a surface of the dielectric layer and defining active layer sidewalls; and

forming a spacer covering a first portion of the exposed dielectric layer surface and substantially spanning one of the active layer sidewalls.

2. The method of claim 1 further comprising forming an etch stop layer over the active layer, wherein the opening is formed through the active layer and the etch stop layer thereby defining etch stop layer sidewalls substantially aligned with the active layer sidewalls, wherein the spacer substantially spans one of the active layer sidewalls and one of the etch stop layer sidewalls.

3. The method of claim 1 further comprising:

cleaning at least a second portion of the exposed dielectric layer surface.

4. The method of claim 3 wherein the cleaning includes chemical etching with an etchant chemistry comprising hydrofluoric acid.

5. The method of claim 3 wherein the cleaning includes plasma etching.

6. The method of claim 5 wherein the plasma etching includes a plasma chemistry comprising fluorine.

7. The method of claim 3 wherein the cleaning includes vapor etching.

8. The method of claim 1 further comprising forming a gate electrode over the active layer.

9. The method of claim 1 further comprising forming a silicide layer over the active layer.

10. The method of claim 1 wherein the spacer comprises silicon dioxide.

11. The method of claim 1 wherein the active layer comprises strained silicon.

12. The method of claim 1 wherein the active layer has a thickness ranging between about 100 Angstroms and about 1000 Angstroms.

13. A microelectronics device, comprising:

a substrate including a structural layer, a dielectric layer located over the structural layer, and an active layer located over the dielectric layer;

an opening extending through the active layer thereby exposing a surface of the dielectric layer and defining active layer sidewalls;

a spacer covering a first portion of the exposed dielectric layer surface and substantially spanning one of the active layer sidewalls; and

a semiconductor device located at least partially over the active layer.

14. The microelectronics device of claim 13 further comprising an etch stop layer located over the active layer, wherein the opening extends through the etch stop layer thereby defining etch stop layer sidewalls substantially aligned with the active layer sidewalls, wherein the spacer substantially spans one of the active layer sidewalls and one of the etch stop layer sidewalls.

15. The microelectronics device of claim 13 further comprising a silicide layer located over the active layer.

16. The microelectronics device of claim 13 wherein the spacer comprises silicon dioxide.

17. The microelectronics device of claim 13 wherein the active layer comprises strained silicon.

18. The microelectronics device of claim 13 wherein the active layer has a thickness ranging between about 100 Angstroms and about 1000 Angstroms.

19. The microelectronics device of claim 13 wherein the active layer comprises:

a silicon layer;

a silicon germanium layer located over the silicon layer; and

a strained silicon layer located over the silicon germanium layer.

20. A integrated circuit device, comprising:

a substrate including a structural layer, a dielectric layer located over the structural layer, and an active layer located over the dielectric layer;

a plurality of openings each extending through the active layer thereby exposing a surface of the dielectric layer and defining a plurality of active layer islands each having sidewalls;

a plurality of spacers each covering a portion of the exposed dielectric layer surface and substantially spanning one of the plurality of active layer sidewalls;

a plurality of semiconductor devices each located at least partially over a corresponding one of the plurality of active layer islands; and

at least one interconnect electrically connecting ones of the plurality of semiconductor devices.

21. The integrated circuit device of claim 20 wherein the dielectric layer comprises diamond.

22. The integrated circuit device of claim 20 wherein the active layer comprises strained silicon.

23. The integrated circuit device of claim 20 wherein the active layer comprises diamond.

24. The integrated circuit device of claim 20 wherein the active layer comprises:

a silicon layer;

a silicon germanium layer located over the silicon layer; and

a strained silicon layer located over the silicon germanium layer.