Arithmetic processing apparatus

• US 20050086276A1
• Filed: 09/08/2004
• Published: 04/21/2005
• Est. Priority Date: 09/11/2003
• Status: Active Grant

• Current Assignee: Godo Kaisha IP Bridge 1 (IP Bridge, Inc.)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Juri, Tatsuro, Masuno, Takashi
• Granted Patent: US 7,412,470 B2
• Time in Patent Office: Days
• US Class Current: 708/201
• CPC Class Codes: G06F 2207/5442 Absolute difference
• CPC Class Codes: G06F 7/544 for evaluating functions by calculation G06F7/4824 takes precedence
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/43 Hardware specially adapted for motion estimation or compensation
• CPC Class Codes: H04N 19/60 using transform coding
• CPC Class Codes: H04N 19/61 in combination with predictive coding

Abstract

The arithmetic processing apparatus of the present invention is an arithmetic processing apparatus that can be reconfigured in accordance with a processing mode and has a plurality of arranged unit arithmetic circuits. Each unit arithmetic circuit includes at least one input terminal, at least one output terminal, a first register which holds data, an adder which calculates a sum of two pieces of data, a second register which holds data, a bit shifter which shifts data left or right, a subtractor which calculates a difference between two pieces of data, an absolute value calculating unit which calculates an absolute value of data, and a path setting unit which sets a path according to the processing mode connecting among these circuit elements.

Claims

1. An arithmetic processing apparatus that can be reconfigured in accordance with a processing mode, comprising a plurality of arranged unit arithmetic circuits,

wherein each of said unit arithmetic circuits includes:

at least one input terminal;

at least one output terminal;

a first register that holds data;

an adder operable to add two pieces of data;

a second register that holds data;

a bit shifter operable to shift data to one of left and right;

a subtractor operable to calculate a difference between two pieces of data;

an absolute value calculating unit operable to calculate an absolute value of data; and

a path setting unit operable to set a connection path according to the processing mode, the connection path connecting among the input terminal, the output terminal, the first register, the adder, the second register, the bit shifter, the subtractor, and the absolute value calculating unit.

2. The arithmetic processing apparatus according to claim 1,

wherein combinations of unit arithmetic circuits form a plurality of arithmetic processing blocks, and

the plurality of arithmetic processing blocks respectively have a unique arithmetic processing function and said arithmetic processing function differs depending on the processing mode.

3. The arithmetic processing apparatus according to claim 2,

wherein the plurality of arithmetic processing blocks include first and second arithmetic processing blocks when the processing mode is a coding mode for a still picture,

the first arithmetic processing block has a partial function for a discrete cosine transform processing using a distributed arithmetic method, and

the second arithmetic processing block has a digital filtering function.

4. The arithmetic processing apparatus according to claim 2,

wherein the plurality of arithmetic processing blocks include first, second and third arithmetic processing blocks when the processing mode is a coding mode for a moving picture using a correlation between moving picture frames,

the first arithmetic processing block has a motion estimation function for a motion compensation interframe prediction coding,

the second arithmetic processing block has a partial function for a discrete cosine transform processing using a distributed arithmetic method, and

the third arithmetic processing block has a digital filtering function.

5. The arithmetic processing apparatus according to claim 2,

wherein said at least one input terminal in each of the unit arithmetic circuits include first to third input terminals,

said at least one output terminal in each of the unit arithmetic circuits includes first and second output terminals,

the path setting unit includes:

a first selector which selects, according to the processing mode, one of the picture data inputted from the second input terminal and the picture data inputted from the third input terminal;

a second selector which selects, according to the processing mode, one of picture data outputted from the first register, picture data outputted from the second register, the picture data inputted from the third input terminal and fixed data; and

a third selector which i) selects, according to the processing mode, one of the picture data outputted from the second register, difference data outputted from the subtractor, and absolute value data outputted from the absolute value calculating unit and ii) outputs the selected data to a first input port of the adder,

the first register holds the picture data inputted from the first input terminal in synchronization with a clock signal,

the adder having the first input port and a second input port i) adds the picture data outputted from the first register and inputted to a second input port and the picture data inputted to the first input port and ii) outputs the added data to the first output terminal,

the second register holds the picture data outputted from the first selector in synchronization with the clock signal,

the bit shifter shifts the picture data outputted from the second register as many as a set number of bits to one of an upper side and a lower side,

the subtractor i) calculates a difference between the picture data outputted from the bit shifter and one of the picture data outputted from the second selector and the fixed data and ii) outputs the difference data to the second output terminal, and

the absolute value calculating unit calculates an absolute value of the difference data outputted from the subtractor.

6. The arithmetic processing apparatus according to claim 5,

wherein the plurality of arithmetic processing blocks include first and second arithmetic processing blocks when the processing mode is a coding mode for a still picture,

the first arithmetic processing block has a partial function for a discrete cosine transform processing using a distributed arithmetic method, and

the second arithmetic processing block has a digital filtering function.

7. The arithmetic processing apparatus according to claim 5,

wherein the plurality of arithmetic processing blocks include first, second and third arithmetic processing blocks when the processing mode is a coding mode for a moving picture using a correlation between moving picture frames,

the first arithmetic processing block has a motion estimation function for a motion compensation interframe prediction coding,

the second arithmetic processing block has a partial function for a discrete cosine transform processing using a distributed arithmetic method, and

the third arithmetic processing block has a digital filtering function.

8. An arithmetic processing apparatus that can be reconfigured in accordance with a processing mode, comprising an arranged plurality of unit arithmetic circuits,

wherein each of the plurality of unit arithmetic circuits includes:

first and second input terminals;

third and fourth input terminals;

a first register operable to hold picture data inputted from the first input terminal in synchronization with a clock signal;

a first selector operable to select and output, according to the processing mode, one of picture data inputted from the second input terminal and picture data inputted from the third input terminal;

an adder having a first input port and a second input port operable to i) add picture data outputted from the first register and inputted to the first input port and picture data inputted to the second input port and ii) output to a first output terminal;

a second register operable to hold the picture data outputted from the first selector in synchronization with the clock signal;

a second selector operable to select and output, according to the processing mode, one of the picture data outputted from the first register, the picture data outputted from the second register, the picture data inputted from the third input terminal, and fixed data;

a bit shifter operable to shift the picture data outputted from the second register as many as a number of set bits to one of upper side and a lower side;

a subtractor operable to i) calculate a difference between the picture data outputted from the bit shifter and one of the picture data outputted from the second selector and the fixed data and ii) output the difference to a second output terminal;

an absolute value calculating unit operable to calculate an absolute value of the difference data outputted from the subtractor; and

a third selector operable to i) select, according to the processing mode, one of the picture data outputted from the second register, the difference data outputted from the subtractor, and the absolute value data outputted from the absolute value calculating unit and ii) output the selected data to the second input port of the adder,

combinations of unit arithmetic circuits form a plurality of arithmetic processing blocks, and

each of the plurality of arithmetic processing blocks has an arithmetic processing function and the arithmetic processing function differs depending on the processing mode, said each one of the arithmetic processing function of said each of the plurality of arithmetic processing blocks being different from each other.

9. The arithmetic processing apparatus according to claim 8,

wherein the processing mode is a coding mode for a still picture, and

the plurality of arithmetic processing blocks include first and second arithmetic processing blocks,

the first arithmetic processing block has a partial function for a discrete cosine transform processing using a distributed arithmetic method, and

the second arithmetic processing block has a digital filtering function.

10. The arithmetic processing apparatus according to claim 8,

wherein the first arithmetic processing block constitutes a butterfly arithmetic circuit.

11. The arithmetic processing apparatus according to claim 9,

wherein in each of unit arithmetic circuits which forms the second arithmetic processing block,

the first selector selects picture data inputted from lower bits of the second input terminal,

the second selector selects picture data inputted from upper bits of the first register,

the third selector selects the picture data outputted from the second register, and

the bit shifter outputs with 0 bit shift.

12. The arithmetic processing apparatus according to claim 9,

wherein the third arithmetic processing block constitutes an arithmetic circuit, the said arithmetic circuit, in synchronization with a clock signal, i) shifting input picture data, in order to multiply the input picture data by a coefficient of n-th power of 2 (n is an integer), to an upper bit side when a sign of n is positive and to a lower bit side when a sign of n is negative as many as a number of bits of the absolute value of n, and ii) sequentially adding the shifted input picture data.

13. The arithmetic processing apparatus according to claim 12,

wherein the third arithmetic processing block has first and second unit arithmetic circuits and a plurality of modules that are arranged in parallel in a row direction,

each of the plurality of modules has as many unit arithmetic circuits connected in a column direction as taps, said unit arithmetic circuits being a unit arithmetic group,

each first output terminal in the unit arithmetic circuit group is connected to a first input terminal of a unit arithmetic circuit that is arranged next in the column direction,

each first selector in the plurality of modules selects the picture data inputted from the third input terminal,

each second selector in the plurality of modules selects the fixed data,

each third selector in the plurality of modules selects the picture data outputted from the subtractor,

the third input terminals in the plurality of modules are connected to each other and the picture data is inputted into said third input terminals,

the first unit arithmetic circuit i) inputs each output data outputted from the plurality of modules that are arranged in parallel into the adder via the first and second registers and ii) outputs the added picture data, and

the second unit arithmetic circuit i) inputs the added picture data into the bit shifter via the second register and ii) outputs an output of the bit shifter as a result of the digital filtering.

14. The arithmetic processing apparatus according to claim 8,

wherein the processing mode is a coding mode for a moving picture using a correlation between moving picture frames,

the plurality of arithmetic processing blocks include first, second and third arithmetic processing blocks,

the first arithmetic processing block has a motion estimation function for a motion compensation interframe prediction coding,

the second arithmetic processing block has a partial function for a discrete cosine transform processing using a distributed arithmetic method, and

the third arithmetic processing block has a digital filtering function.

15. The arithmetic processing apparatus according to claim 14,

wherein the first arithmetic processing block constitutes an arithmetic circuit which calculates a sum of difference absolute values, and

the second arithmetic processing block constitutes a butterfly arithmetic circuit.

16. The arithmetic processing circuit according to claim 14,

wherein in each of the unit arithmetic circuits which constitute the second arithmetic processing block,

the first selector selects picture data inputted from lower bits of the second input terminal,

the second selector selects inputted from upper bits of the first register,

the third selector selects the picture data inputted from the second register, and

the bit shifter outputs with 0 bit shift.

17. The arithmetic processing apparatus according to claim 14,

wherein in each of unit arithmetic circuits which constitutes the first arithmetic processing block,

the first selector selects picture data to be compared that is inputted from the second input terminal,

the second selector selects picture data for reference that is inputted from the third input terminal,

the third selector selects absolute value data outputted from the absolute value calculating unit, and

the bit shifter outputs with 0 bit shift.

18. The arithmetic processing apparatus according to claim 14,

wherein the first arithmetic processing block has as many number of the unit arithmetic circuits arranged in a row direction as a number of pixels on which a motion estimation is performed, and

picture data for reference is inputted while shifting a position in a column direction.

19. The arithmetic processing apparatus according to claim 18,

wherein the plurality of the first arithmetic processing blocks are arranged in parallel in the row direction, and

the picture data for reference which is shifted by one pixel each in the column direction is inputted into the plurality of first arithmetic processing blocks.

20. The arithmetic processing apparatus according to claim 18,

wherein the first arithmetic processing block has a plurality of modules that are arranged in parallel in the row direction,

each of the plurality of modules is constituted by connecting as many said unit arithmetic circuits as a number of pixels in the column direction,

pixel data for reference which constitutes the picture data for reference is commonly inputted to the third input terminals in the plurality of modules, and

the first input terminals in the plurality of modules are connected to a first output of an adjacent unit arithmetic circuit.

21. The arithmetic processing apparatus according to claim 14, wherein the third arithmetic processing block constitutes an arithmetic circuit, the said arithmetic circuit, in synchronization with a clock signal, i) shifting input picture data, in order to multiply the input picture data by a coefficient of n-th power of 2 (n is an integer), to an upper bit side when a sign of n is positive and to a lower bit side when a sign of n is negative as many as a number of bits of the absolute value of n, and ii) sequentially adding the shifted input picture data.

22. The arithmetic processing apparatus according to claim 21,

wherein the third arithmetic processing block has first and second unit arithmetic circuits and a plurality of modules that are arranged in parallel in a row direction,

each of the plurality of modules has as many unit arithmetic circuits connected in a column direction as taps, said unit arithmetic circuits being a unit arithmetic group,

each first output terminal in the unit arithmetic circuit group is connected to a first input terminal of a unit arithmetic circuit that is arranged next in the column direction,

each first selector in the plurality of modules selects the picture data inputted from the third input terminal,

each second selector in the plurality of modules selects the fixed data,

each third selector in the plurality of modules selects the picture data outputted from the subtractor,

the third input terminals in the plurality of modules are connected to each other and the picture data is inputted into said third input terminals,

the first unit arithmetic circuit i) inputs each output data outputted from the plurality of modules that are arranged in parallel into the adder via the first and second registers and ii) outputs the added picture data, and

the second unit arithmetic circuit i) inputs the added picture data into the bit shifter via the second register and ii) outputs an output of the bit shifter as a result of the digital filtering.

23. The arithmetic processing apparatus according to claim 14,

wherein combinations of the unit arithmetic circuits form a plurality of arithmetic processing blocks, and

the plurality of arithmetic processing blocks respectively have a unique arithmetic processing function and the arithmetic processing function differs depending on the processing mode.

24. The arithmetic processing apparatus according to claim 23,

wherein the plurality of arithmetic processing blocks includes first, second and third arithmetic processing blocks when the processing mode is a coding mode for a moving picture using a correlation between moving picture frames,

the first arithmetic processing block has a motion estimation function in a motion compensation interframe prediction coding,

the second arithmetic block has a partial function for a discrete cosine transform processing using a distributed arithmetic method, and

the third arithmetic processing block has a digital filtering function.

25. A semiconductor device that can be reconfigured in accordance with a processing mode, comprising a plurality of arranged unit arithmetic circuits,

wherein each of the plurality of unit arithmetic circuits include:

at least one input terminal;

at least one output terminal;

a first register that holds data;

an adder operable to add two pieces of data;

a second register that holds data;

a bit shifter operable to shift data to one of left and right;

a subtractor operable to calculates a difference between two pieces of data;

an absolute value calculating unit operable to calculate an absolute value of data; and

a path setting unit operable to set a path according to the processing mode, the path connecting among the input terminal, the output terminal, the first register, the adder, the second register, the bit shifter, the subtractor, and the absolute value calculating unit.