Table look-up for control of instruction execution
First Claim
1. A microprocessor chip, comprising:
- instruction pipeline circuitry;
instruction classification circuitry responsive to execution of instructions executed by the instruction pipeline circuitry to classify the executed instructions into a small number of classes and record a classification code value;
an on-chip table, each entry of the on-chip table corresponding to a range of addresses of a memory of the computer and designed to hold a statistical assessment of a value of consulting an off-chip table in a memory of the computer;
lookup circuitry designed to fetch an entry from a on-chip table as part of the basic instruction processing cycle of the microprocessor;
a mask whose value is set at least in part by a timer;
pipeline control circuitry designed to consult the on-chip table and to control processing of instructions by the instruction pipeline circuitry as part of the basic instruction processing cycle of the microprocessor, depending, at least in part, on the value of the on-chip table entry corresponding to the address of an instruction processed by the instruction pipeline circuitry, the current value of the mask, and the recorded classification code; and
control circuitry and/or software designed to cooperate with the instruction pipeline circuitry and pipeline control circuitry to control operation of the instruction pipeline circuitry based on consultation of the off-chip table after a favorable value is obtained from the on-chip table.
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Accused Products
Abstract
A microprocessor chip has instruction pipeline circuitry, and instruction classification circuitry that classifies instructions as they are executed into a small number of classes and records a classification code value. An on-chip table has entries corresponding to a range of addresses of a memory and designed to hold a statistical assessment of a value of consulting an off-chip table in a memory of the computer. Lookup circuitry is designed to fetch an entry from the on-chip table as part of the basic instruction processing cycle of the microprocessor. A mask has a value set at least in part by a timer. The instruction pipeline circuitry is controlled based on the value of the on-chip table entry corresponding to the address of instructions processed, the current value of the mask, the recorded classification code, and the off-chip table.
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Citations
65 Claims
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1. A microprocessor chip, comprising:
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instruction pipeline circuitry;
instruction classification circuitry responsive to execution of instructions executed by the instruction pipeline circuitry to classify the executed instructions into a small number of classes and record a classification code value;
an on-chip table, each entry of the on-chip table corresponding to a range of addresses of a memory of the computer and designed to hold a statistical assessment of a value of consulting an off-chip table in a memory of the computer;
lookup circuitry designed to fetch an entry from a on-chip table as part of the basic instruction processing cycle of the microprocessor;
a mask whose value is set at least in part by a timer;
pipeline control circuitry designed to consult the on-chip table and to control processing of instructions by the instruction pipeline circuitry as part of the basic instruction processing cycle of the microprocessor, depending, at least in part, on the value of the on-chip table entry corresponding to the address of an instruction processed by the instruction pipeline circuitry, the current value of the mask, and the recorded classification code; and
control circuitry and/or software designed to cooperate with the instruction pipeline circuitry and pipeline control circuitry to control operation of the instruction pipeline circuitry based on consultation of the off-chip table after a favorable value is obtained from the on-chip table.
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2. A microprocessor chip, comprising:
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instruction pipeline circuitry;
lookup circuitry designed to fetch an entry from a lookup structure as part of the basic instruction processing cycle of the microprocessor, each entry of the lookup structure being associated with a corresponding address range accessed by the microprocessor;
a mask whose value is set at least in part by a timer;
pipeline control circuitry designed to control processing of instructions by the instruction pipeline circuitry as part of the basic instruction processing cycle of the microprocessor, depending, at least in part, on the value of the entry corresponding to the address range in which lies an instruction processed by the instruction pipeline circuitry, and the current value of the mask. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A microprocessor chip, comprising:
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instruction pipeline circuitry;
instruction classification circuitry responsive to execution of instructions executed by the instruction pipeline circuitry to classify the executed instructions into a small number of classes and record a classification code value;
lookup circuitry designed to fetch an entry from a lookup structure as part of the basic instruction processing cycle of the microprocessor, each entry of the lookup structure being associated with a corresponding address range accessed by the microprocessor; and
pipeline control circuitry designed to control processing of instructions by the instruction pipeline circuitry as part of the basic instruction processing cycle of the microprocessor, depending, at least in part, on the value of the entry corresponding to the address range in which the instruction address lies, and the recorded classification code. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A microprocessor chip, comprising:
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instruction pipeline circuitry;
an on-chip table, each entry of the on-chip table corresponding to a respective class of event occurring in the microprocessor, and designed to hold an approximate and inexact evaluation of a portion of the microprocessor machine state for control of the circuitry; and
pipeline control circuitry cooperatively designed with the instruction pipeline circuitry to control processing of instructions by the instruction pipeline circuitry as part of the basic instruction processing cycle of the microprocessor, based on consultation of the on-chip table. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36)
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37. A microprocessor chip, comprising:
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instruction pipeline circuitry;
an on-chip table, each entry of the on-chip table corresponding to a class of event occurring the in the microprocessor and designed to control consultation of an off-chip table in a memory accessed by the microprocessor when an event of the class occurs;
pipeline control circuitry cooperatively designed with the instruction pipeline circuitry to consult the on-chip table as part of the basic instruction processing cycle of the microprocessor, as the classified events occur; and
control circuitry and/or software designed to cooperate with the instruction pipeline circuitry and pipeline control circuitry to affect a manipulation of data or transfer of control defined for the event in the instruction pipeline circuitry based on consultation of the off-chip table after a favorable value is obtained from the on-chip table. - View Dependent Claims (38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48)
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49. A method, comprising the steps of:
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executing a computer program in instruction pipeline circuitry of a microprocessor, the microprocessor having lookup circuitry designed to fetch an entry from a lookup structure as part of the basic instruction processing cycle of the microprocessor, entries of the lookup structure being indexed by a corresponding address ranges of addresses generated by the microprocessor;
as part of the basic instruction processing cycle of the microprocessor, controlling processing of instructions by the instruction pipeline circuitry based at least in part on the value of the entry corresponding to the address range in which lies an instruction processed by the instruction pipeline circuitry, and the current value of a mask, the mask having a value set at least in part by a timer. - View Dependent Claims (50, 51)
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52. A method, comprising the steps of:
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storing information in a slow representation in a computer memory;
generating a fast representation of portions of the information in the computer memory;
dividing the slow representation of the information into spatial blocks;
classifying elements of the information into logical classes; and
forming a correspondence map from elements of the slow representation to corresponding elements in the fast representation, the correspondence map noting whether an element of the information has an extant fast representation, and if extant, providing an access key to the corresponding fast representation, the correspondence map being indexed by the spatial division and the logical classification of the information elements. - View Dependent Claims (53, 54, 55, 56, 57, 58, 59)
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60. A method, comprising the steps of:
as part of the basic instruction processing cycle of a microprocessor, controlling processing of instructions by instruction pipeline circuitry of a microprocessor, based on consultation of a table, the table being indexed by a respective class of event occurring in the microprocessor, and designed to hold an approximate and inexact evaluation of a portion of the microprocessor machine state. - View Dependent Claims (61, 62)
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63. A method, comprising the steps of:
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as part of the basic instruction processing cycle of a microprocessor, consulting an on-chip table located in the microprocessor, entries of the on-chip table being indexed by a class of event occurring the in the microprocessor, the consulting occurring as the classified events occur; and
after a favorable value is obtained from the on-chip table, consulting an off-chip table in a memory accessed by the microprocessor; and
affecting a manipulation of data or transfer of control defined for the classified event based on consultation of the off-chip table. - View Dependent Claims (64, 65)
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Specification