Automatic power savings stand-by control for non-volatile memory

• US 20050086548A1
• Filed: 11/15/2002
• Published: 04/21/2005
• Est. Priority Date: 11/15/2002
• Status: Active Grant

• Current Assignee: Intel NDTM US LLC (Intel Corporation)
• Original Assignee: Intel Corporation
• Inventors: Haid, Christopher John, Carrieri, Enrico David
• Granted Patent: US 7,549,066 B2
• Time in Patent Office: Days
• US Class Current: 713/320
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A non-volatile memory array such as a flash memory array may include a power savings circuit to control a stand-by mode of the non-volatile memory array. The power savings circuit may cause a placement of the non-volatile memory array into a stand-by mode in the absence of activity on at least one or more inputs of the non-volatile memory array. Power may be saved automatically without processor intervention by reducing the operating current of the non-volatile memory array. The automatic power savings circuit may provide a chip enable output to an input of stand-by circuitry to control the operation of the standby circuitry without requiring an explicit stand-by command from a processor.

Claims

1. An apparatus, comprising:

a non-volatile memory array; and

a power saving circuit to place said non-volatile memory array into a stand-by mode in the event there is an absence of activity on an input to said non-volatile memory array.

2. An apparatus as claimed in claim 1, wherein said power saving circuit is configured to place said non-volatile memory array in a stand-by mode without requiring processor intervention.

3. An apparatus as claimed in claim 1, the input including an address line of said non-volatile memory array.

4. An apparatus as claimed in claim 1, wherein the absence of activity includes an absence of address activity from a processor.

5. An apparatus as claimed in claim 1, wherein said power saving circuit to place said non-volatile memory array in a stand-by mode in the event of an absence of activity at an input to said non-volatile memory array after a predetermined period of time.

6. An apparatus as claimed in claim 1, said power saving circuit including:

a delay element to receive a chip select signal for said non-volatile memory array;

at least one address transition detector to detect an absence of activity on an address line of said non-volatile memory array; and

a logic circuit to receive an output from the delay element and the at least one address transition detector, to provide a chip enable output to control the stand-by mode.

7. A method, comprising:

determining whether there is an absence of activity on an input to a non-volatile memory array; and

in the event there is an absence of activity, placing the non-volatile memory array into a stand-by mode.

8. A method as claimed in claim 7, said placing including providing a chip enable output to control the stand-by mode.

9. A method as claimed in claim 7, said placing including placing the non-volatile memory array into a stand-by mode without requiring a command provided by a processor.

10. A method as claimed in claim 7, said determining including determining whether there is activity on an address input of the non-volatile memory array.

11. A method as claimed in claim 7, further comprising determining whether the non-volatile memory array is selected, and executing said placing when a chip select input indicates the non-volatile memory array is not selected.

12. A method as claimed in claim 7, further comprising determining whether the memory array is selected with a cell select input, introducing a delay on the cell select input, and executing said placing when the cell select input indicates the non-volatile memory array is not selected.

13. A method comprising:

providing a chip enable output to input of a stand-by circuit of a non-volatile memory array to control a stand-by mode of the memory array when a chip enable output indicates the memory array is not enabled, when there is an absence of activity on at least one address input of the non-volatile memory array, or when a cell select input indicates the non-volatile memory array is not selected, to cause the stand-by circuit to activate a stand-by mode for the non-volatile memory array.

14. A method as claimed in claim 13, further comprising introducing a delay on the cell select input.

15. An apparatus, comprising:

a wireless transceiver;

a non-volatile memory array; and

a power saving circuit to control a stand-by mode of the non-volatile memory array.

16. An apparatus as claimed in claim 15, said power saving circuit to control the operation of the stand-by mode without requiring processor intervention.

17. An apparatus as claimed in claim 15, said power saving circuit to provide a chip enable output to control the operation of the stand-by mode based on at least one or more of a chip enable input, an address input, and a cell select input provided to said non-volatile memory array.

18. An apparatus as claimed in claim 15, said power saving circuit to activate a stand-by mode when said power saving circuit detects an absence of activity on at least one input to said non-volatile memory array.

19. An apparatus as claimed in claim 15, said power saving circuit including at least one address transition detector for detecting an absence of activity on at least one input to said non-volatile memory array.