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Method for printed circuit board panelization

  • US 20050086616A1
  • Filed: 10/15/2003
  • Published: 04/21/2005
  • Est. Priority Date: 10/15/2003
  • Status: Abandoned Application
First Claim
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1. A method for performing Printed Circuit Board (PCB) panel optimization, comprising the steps of:

  • performing a panel dimension loop that goes through a plurality of possible panel dimensions;

    performing an array length loop that goes through a plurality of array lengths;

    performing an array width loop that goes through a plurality of array widths; and

    calculating a panel efficiency factor for each iteration of each of the loops in order to determine a panel layout.

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