Method for manufacturing a power bus on a chip

• US 20050086625A1
• Filed: 10/27/2004
• Published: 04/21/2005
• Est. Priority Date: 02/10/1992
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Lin, Chong Ming, Hoang, Hy, Chuang, Tatao, Long, Tran
• Granted Patent: US 7,103,867 B2
• Time in Patent Office: Days
• US Class Current: 716/54
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for manufacturing a power bus on a chip, where the power bus has slits generated therein. The present invention relates to a method to manufacture a power bus in which the reference to a layout data base shows the coordinate location of the power buses in the chip. A height and width for the power bus is calculated based on its coordinates. Based on the height and width of the power buses and the predetermined size and spacing between power slits, a number of power slits to be generated is determined. These power slits are then generated by adding the power slits to the power bus in the coordinates of the layout database. The method of the present invention also generates power slits for use in manufacturing power buses on a chip for cases in which the power buses overlap.

Claims

1. A method for manufacturing a power bus on a chip, said method comprising the steps of:

(a) locating said power bus on said chip;

(b) determining the number of power slits to be generated in said power bus, including the steps of,

(i) determining a width for said power bus and a length for said power bus,

(ii) dividing said width by a maximum width of the power slits plus a first spacing distance between the power slits, resulting in a first number indicating how many power slit(s) to generate in a width direction of said bus, and

(iii) dividing said length by a minimum length of the power slits plus a second spacing distance between the power slits, resulting in a second value indicating how many power slit(s) to generate in a length direction of said bus; and

(c) generating said plurality of power slits on said power bus according to the results of said steps (b)(i) and (b)(ii) utilizing said first and second spacing distance between each of said power slits in said width and said length directions of said power bus, respectively.

2-11. -11. (canceled).