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Transferring execution from one instruction stream to another

  • US 20050086650A1
  • Filed: 12/02/2004
  • Published: 04/21/2005
  • Est. Priority Date: 01/28/1999
  • Status: Active Grant
First Claim
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1. A computer, comprising:

  • instruction pipeline circuitry designed to effect interpretation of computer instructions under two instruction set architectures alternately;

    a binary translator programmed to translate at least a selected portion of a computer program from a lower-performance one of the instruction set architectures to a higher-performance one of the instruction set architectures;

    pipeline control circuitry cooperatively designed with the instruction pipeline circuitry to initiate a query, when about to execute a program region coded in a lower-performance one of the instruction set architectures in the instruction pipeline circuitry, the query inquiring whether a program region coded in the higher-performance instruction set architectures exists, the higher-performance region being logically equivalent to the lower-performance program region, the pipeline control circuitry being effective to initiate the determination with neither a query nor a transfer of control to the lower-performance region being coded into the lower-performance region;

    circuitry and/or software designed to abort the execution of the about-to-be-executed instruction when the higher-performance region exists, and to transfer execution control to the higher-performance region, without an alternation to effect the transfer being made to the lower-performance binary object code; and

    circuitry and/or software designed to reestablish execution of the lower-performance region after execution of the higher-performance region, execution of the lower-performance region being reestablished at a point downstream from the aborted instruction, in a context logically equivalent to that which would have prevailed had the code of the lower-performance region been allowed to proceed.

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