Transferring execution from one instruction stream to another

• US 20050086650A1
• Filed: 12/02/2004
• Published: 04/21/2005
• Est. Priority Date: 01/28/1999
• Status: Active Grant

• Current Assignee: Advanced Silicon Technologies LLC
• Original Assignee: ATI International SRL (Advanced Micro Devices, Inc.)
• Inventors: Reese, David L., Hohensee, Paul H., Purcell, Stephen C., Yates, John S. Jr., Van Dyke, Korbin S.
• Granted Patent: US 8,121,828 B2
• Time in Patent Office: Days
• US Class Current: 717/139
• CPC Class Codes: G06F 9/45533 Hypervisors; Virtual machine monitors

Abstract

A computer has instruction pipeline circuitry capable of executing two instruction set architectures (ISA'"'"'s). A binary translator translates at least a selected portion of a computer program from a lower-performance one of the ISA'"'"'s to a higher-performance one of the ISA'"'"'s. Hardware initiates a query when about to execute a program region coded in the lower-performance ISA, to determine whether a higher-performance translation exists. If so, the about-to-be-executed instruction is aborted, and control transfers to the higher-performance translation. After execution of the higher-performance translation, execution of the lower-performance region is reestablished at a point downstream from the aborted instruction, in a context logically equivalent to that which would have prevailed had the code of the lower-performance region been allowed to proceed.

Claims

1. A computer, comprising:

instruction pipeline circuitry designed to effect interpretation of computer instructions under two instruction set architectures alternately;

a binary translator programmed to translate at least a selected portion of a computer program from a lower-performance one of the instruction set architectures to a higher-performance one of the instruction set architectures;

pipeline control circuitry cooperatively designed with the instruction pipeline circuitry to initiate a query, when about to execute a program region coded in a lower-performance one of the instruction set architectures in the instruction pipeline circuitry, the query inquiring whether a program region coded in the higher-performance instruction set architectures exists, the higher-performance region being logically equivalent to the lower-performance program region, the pipeline control circuitry being effective to initiate the determination with neither a query nor a transfer of control to the lower-performance region being coded into the lower-performance region;

circuitry and/or software designed to abort the execution of the about-to-be-executed instruction when the higher-performance region exists, and to transfer execution control to the higher-performance region, without an alternation to effect the transfer being made to the lower-performance binary object code; and

circuitry and/or software designed to reestablish execution of the lower-performance region after execution of the higher-performance region, execution of the lower-performance region being reestablished at a point downstream from the aborted instruction, in a context logically equivalent to that which would have prevailed had the code of the lower-performance region been allowed to proceed.

2. A computer, comprising:

instruction pipeline circuitry;

pipeline control circuitry cooperatively designed with the instruction pipeline circuitry to initiate, when about to execute a program region coded in a lower-performance binary object code representation, a query whether a program region coded in a higher-performance binary object code representation exists, the higher-performance region being logically equivalent to the lower-performance program region; and

circuitry and/or software to transfer execution control to the higher-performance region, without an alternation to effect the transfer being made to the lower-performance binary object code.

3. The computer of claim 2, wherein the instruction pipeline circuitry is designed to effect interpretation of computer instructions under two instruction set architectures alternately, and the two binary object code representations are coded in the two instruction set architectures, respectively.

4. The computer of claim 2, wherein instructions of the higher-performance region were generated by translating binary instructions of the lower-performance region.

5. The computer of claim 2:

wherein the query is initiated as part of executing an instruction from the lower-performance binary object code representation;

and further comprising circuitry and/or software designed to abort the execution of the instruction when the higher-performance binary object code representation exists, and to transfer control to the higher-performance binary object code representation.

6. The computer of claim 2, further comprising:

circuitry and/or software designed to reestablish execution of the lower-performance region after execution of the higher-performance region, execution of the lower-performance region being reestablished at a point downstream from the point from which control was transferred to the higher-performance region, in a context logically equivalent to that which would have prevailed had the code of the lower-performance region been allowed to proceed.

7. The computer of claim 2,

wherein the pipeline control circuitry is designed to heuristically and approximately-correctly recognize that the higher-performance region exists;

and further comprising software to make a final evaluation of whether the higher-performance region exists.

8. The computer of claim 2, wherein the transfer of execution control to the higher-performance region is effected by an architecturally-visible alteration of a program counter.

9. The computer of claim 2, wherein the region about to be executed is entered by a transfer of control instruction.

10. A method, comprising the steps of:

translating at least a selected portion of a computer program from a first binary object code representation to a second binary object code representation;

during execution of the first binary object code representation of the program on a computer, recognizing that execution has entered the selected portion, the recognizing being initiated by basic instruction execution of the computer, without an alternation to effect the transfer being made to the first binary object code; and

in response to the recognition, transferring control to the translation in the first binary object code representation.

11. The method of claim 10, wherein the first and second binary object code representations are two different instruction set architectures, and the computer includes instruction pipeline circuitry designed to effect interpretation of computer instructions under the two instruction set architectures alternately.

12. The method of claim 10, further comprising the steps of:

as part of executing an instruction of the first binary object code representation, recognizing that the translated first binary object code representation exists in correspondence with the executing instruction; and

aborting the execution of the instruction of the first binary object code representation.

13. The method of claim 10, wherein the recognizing is triggered by a heuristic, approximately-correct analysis performed in circuitry of the computer.

14. A computer, comprising:

instruction pipeline circuitry;

a binary translator programmed to translate at least a selected portion of a computer program from a first binary object code representation to a second binary object code representation;

pipeline control circuitry cooperatively designed with the instruction pipeline circuitry to initiate a determination of whether to transfer control from an execution of the first binary object code representation of the program to the second, and effective to initiate the determination, without an alternation to effect the transfer being made to the first binary object code.

15. The method of claim 14, wherein instructions of the second binary object code representation are coded in a different instruction set architecture than instructions of the first binary object code representation.

16. The computer of claim 14, wherein:

the instruction pipeline circuitry is designed to effect interpretation of computer instructions under two instruction set architectures alternately; and

the binary translator is programmed to translate the selected portion from a first of the two instruction set architectures to a second of the two instruction set architectures.

17. A method, comprising the steps of:

as part of executing an instruction on a computer, recognizing that an alternate binary object code representation of the instruction exists, the recognizing being initiated without an instruction to transfer control to the alternate binary object code representation, or otherwise altering the binary object code to effect the transfer;

when an alternate binary object code representation exists, aborting the execution of the instruction; and

transferring control to the alternate binary object code representation.

18. The method of claim 17, wherein the instruction and alternate binary object code representation are coded in two different instruction set architectures, and the computer includes instruction pipeline circuitry designed to effect interpretation of computer instructions under the two instruction set architectures alternately.

19. The method of claim 17, wherein the recognizing is triggered by a heuristic, approximately correct analysis performed in circuitry of the computer.

20. The method of claim 17, further comprising the step of:

reestablishing execution of an instruction stream of the aborted instruction after execution of an instruction stream of the alternate binary object code representation, execution of the aborted instruction stream being reestablished at a point downstream from the aborted instruction, in a context logically equivalent to that which would have prevailed had the aborted instruction stream been allowed to proceed.

21. The method of claim 17, further comprising the step of:

initiating the recognition by consulting a content-addressable memory addressed by a program counter address of the instruction to be executed.

22. The method of claim 21, wherein the content-addressable memory is an instruction translation look-aside buffer.

23. The method of claim 21, wherein the content-addressable memory is loaded from a memory table parallel to and distinct from page mapping tables used by a virtual memory manager.

24. A computer, comprising:

instruction pipeline circuitry;

pipeline control circuitry cooperatively designed with the instruction pipeline circuitry effective to recognize, as part of executing an instruction, that an alternate binary object code representation of the instruction exists, the recognizing being initiated without an alternation to effect the transfer being made to the binary object code representation of which the instruction is a part; and

circuitry and/or software designed to abort the execution of the instruction when the alternate binary object code representation exists, and to transfer control to the alternate binary object code representation.

25. The computer of claim 24, wherein the instruction pipeline circuitry is designed to effect interpretation of computer instructions under two instruction set architectures alternately, and the two binary object code representations are coded in the two instruction set architectures, respectively.

26. The computer of claim 25, further comprising a binary translator programmed to translate at least a selected portion of the program of the executed instruction to have generated the alternate binary object code representation.

27. The computer of claim 26:

wherein the instruction pipeline circuitry is designed to effect interpretation of computer instructions under two instruction set architectures alternately;

and further comprising a binary translator programmed to translate at least a selected portion of the instruction stream of the executed instruction from a first of the two instruction set architectures to generate the alternate binary object code representation in a second of the two instruction set architectures.

28. The computer of claim 24, wherein:

the instruction pipeline circuitry is designed to effect interpretation of computer instructions under two instruction set architectures alternately; and

the binary translator is programmed to translate the selected portion from a first of the two instruction set architectures to a second of the two instruction set architectures.

29. The computer of claim 24, further comprising:

lookup circuitry designed to fetch an entry from a lookup structure, each entry of the lookup structure being associated with a corresponding address range of a memory of the computer; and

a mask whose value is set at least in part by a timer;

wherein the pipeline control circuitry is further designed to control processing of instructions by the instruction pipeline circuitry depending, at least in part, on the value of the entry corresponding to the address range in which lies an instruction processed by the instruction pipeline circuitry, and the current value of the mask.

30. The computer of claim 24, further comprising:

instruction classification circuitry responsive to execution of instructions executed by the instruction pipeline circuitry to classify the executed instructions into a small number of classes and record a classification code value; and

lookup circuitry designed to fetch an entry from a lookup structure, each entry of the lookup structure being associated with a corresponding address range of a memory of the computer;

wherein the pipeline control circuitry is further designed to control processing of instructions by the instruction pipeline circuitry depending, at least in part, on the value of the entry corresponding to the address range in which lies an instruction processed by the instruction pipeline circuitry, and the recorded classification code.

31. The computer of claim 24, further comprising:

lookup circuitry designed to fetch an entry from a lookup structure, each entry of the lookup structure being associated with a corresponding address range of a memory of the computer, each entry of the lookup structure designed to hold an evaluation of a portion of the computer machine state for control of the circuitry;

wherein the pipeline control circuitry is further designed with the instruction pipeline circuitry to control processing of instructions by the instruction pipeline circuitry based on consultation of the on-chip table as part of the basic instruction processing cycle of the microprocessor.

32. The computer of claim 24:

further comprising lookup circuitry designed to fetch an entry from a lookup structure onboard a microprocessor chip of the computer, each entry of the lookup structure being associated with a corresponding class of event occurring in the computer, each entry of the lookup structure designed to control consultation of an off-chip table in a memory of the computer when an event of the class occurs;

wherein the pipeline control circuitry is further designed with the instruction pipeline circuitry to consult the on-chip table;

and further comprising control circuitry and/or software designed to cooperate with the instruction pipeline circuitry and pipeline control circuitry to control operation of the instruction pipeline circuitry based on consultation of the off-chip table after a favorable value is obtained from the on-chip table.

33. A method, comprising the steps of:

during execution of a program on instruction pipeline circuitry of a computer, initiating a determination of whether to transfer control from a first instruction stream in execution by the instruction pipeline circuitry to a second instruction stream, without an alteration to effect the transfer being made to the first instruction stream; and

reestablishing execution of the first instruction stream after execution of the second instruction stream, execution of the first instruction stream being reestablished at a point downstream from the point at which control was seized, in a context logically equivalent to that which would have prevailed had the code of the first instruction stream been allowed to proceed.

34. The method of claim 33, wherein the first and second instruction streams are coded in two different instruction set architectures, and the computer includes instruction pipeline circuitry designed to effect interpretation of computer instructions under the two instruction set architectures alternately.

35. The method of claim 33, wherein the second instruction stream was generated by translating binary instructions of the first instruction stream.

36. The method of claim 33, wherein the determining comprises a heuristic, approximately-correct analysis performed in circuitry of the computer.

37. A method, comprising the steps of:

while executing a program on a computer, when about to execute a program region coded in a lower-performance binary object code representation, querying whether a program region coded in a higher-performance binary object code representation exists, the higher-performance region being logically equivalent to the lower-performance program region, the query being initiated in hardware; and

transferring execution control to the higher-performance region, without an alteration being made to the lower-performance binary object code in order to effect the transfer.

38. The method of claim 37, further comprising the step of:

evaluating whether to transfer control from the first image to the second based on control variables of the computer.

39. The method of claim 37, wherein:

the first image is coded in an instruction set non-native to the computer, for hardware emulation in the computer; and

the second image is generated from the first image by a binary translator.

40. The method of claim 39, wherein:

the binary translator optimizes the second image for increased execution speed, while accepting some risk of execution differing from the execution of the non-native program on its native instruction set architecture.