Method of fabricating circular or angular spiral MIM capacitors

• US 20050086780A1
• Filed: 10/23/2003
• Published: 04/28/2005
• Est. Priority Date: 10/23/2003
• Status: Abandoned Application

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Inventors: Chu, Sanford, Verma, Purakh Raj, Ng, Chit Hwei, Shao, Kai, Zheng, Jia Zhen
• Application Number:
  US10/692,029
• Publication Number:
  US 20050086780A1
• Time in Patent Office: Days
• US Class Current: 29/25.410
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: Y10T 29/43 Electric condenser making
• CPC Class Codes: Y10T 29/435 Solid dielectric type
• CPC Class Codes: Y10T 29/49165 by forming conductive walled aperture in base

Abstract

A method of forming a capacitor comprising the following steps. A substrate having a lower low-k dielectric layer formed thereover is provided with the lower low-k dielectric layer having a dielectric constant of less than about 3.0. Metal vertical electrode plates are formed within the lower low-k dielectric layer so that the adjacent metal vertical electrode plates have lower low-k dielectric layer portions therebetween. The lower low-k dielectric layer portions between the adjacent metal vertical electrode plates are replaced with high-k dielectric material trench portions having a dielectric constant of greater than about 3.0.

Claims

1. A method of forming a capacitor, comprising the steps of:

providing a substrate having a lower low-k dielectric layer formed thereover;

the lower low-k dielectric layer having a dielectric constant of less than about 3.0;

forming metal vertical electrode plates within the lower low-k dielectric layer such that adjacent metal vertical electrode plates have lower low-k dielectric layer portions therebetween; and

replacing the lower low-k dielectric layer portions between the adjacent metal vertical electrode plates with high-k dielectric material trench portions;

the high-k dielectric material trench portions having a dielectric constant of greater than about 3.0.

2. The method of claim 1, wherein the substrate is a semiconductor wafer.

3. The method of claim 1, wherein the lower low-k dielectric layer has a thickness of from about 2000 to 50,000 Å

.

4. The method of claim 1, wherein the lower low-k dielectric layer has a thickness of from about 5000 to 10,000 Å

.

5. The method of claim 1, wherein the lower low-k dielectric layer is comprised of TEOS, FTEOS, Coral™

, Black Diamond™

or an organic material.

6. The method of claim 1, wherein the lower low-k dielectric layer is comprised of an organic material.

7. The method of claim 1, wherein the high-k dielectric material trench portions are comprised of SiN, Ta_xO_y, Hf_xO_y, Ti_xO_y, Al₂O₃, Ta_xAl_yO_z, Ti_x,Al_yO_z, SiO₂, Ta_xN_yO_z, Ti_xN_yO_z or a non-conductive oxidized refractory metal.

8. The method of claim 1, wherein the high-k dielectric material trench portions are comprised of a low leakage and high breakdown material.

9. The method of claim 1, wherein the high-k dielectric material trench portions have a dielectric constant of from about 7.0 to 50.0.

10. The method of claim 1, wherein the metal vertical electrode plates are comprised of copper or tungsten.

11. The method of claim 1, wherein the metal vertical electrode plates are comprised of copper.

12. The method of claim 1, including the step of lining the metal vertical electrode plates with respective metal barrier layers.

13. The method of claim 1, including the step of lining the metal vertical electrode plates with respective metal barrier layers comprised of Ta or TaN.

14. The method of claim 1, including the step of lining the metal vertical electrode plates with respective metal barrier layers comprised of Ta/TaN.

15. The method of claim 1, including the steps of:

forming an upper low-k dielectric material layer over the metal vertical electrode plates;

the upper low-k dielectric material layer having a dielectric constant of less than about 3.0; and

forming respective via structures within the upper low-k dielectric material layer in electrical communication with the respective metal vertical electrode plates.

16. The method of claim 1, including the steps of:

forming an upper low-k dielectric material layer over the metal vertical electrode plates;

the upper low-k dielectric material layer having a dielectric constant of less than about 3.0; and

forming respective lined via structures within the upper low-k dielectric material layer in electrical communication with the respective metal vertical electrode plates.

17. The method of claim 1, including the steps of:

forming an upper low-k dielectric material layer over the metal vertical electrode plates to a thickness of from about 2000 to 50,000 Å

;

the upper low-k dielectric material layer having a dielectric constant of less than about 3.0; and

forming respective via structures within the upper low-k dielectric material layer in electrical communication with the respective metal vertical electrode plates;

the via structures being comprised of copper or tungsten.

18. The method of claim 1, including the steps of:

forming an upper low-k dielectric material layer over the metal vertical electrode plates to a thickness of from about 5000 to 10,000 Å

;

the upper low-k dielectric material layer having a dielectric constant of less than about 3.0; and

forming respective via structures within the upper low-k dielectric material layer in electrical communication with the respective metal vertical electrode plates;

the via structures being comprised of copper.

19. The method of claim 1, including the steps of:

forming an etch stop layer over the metal vertical electrode plates;

forming an upper low-k dielectric material layer over the etch stop layer;

the upper low-k dielectric material layer having a dielectric constant of less than about 3.0; and

forming respective via structures within the etch stop layer and the upper low-k dielectric material layer in electrical communication with the respective metal vertical electrode plates.

20. The method of claim 1, including the steps of:

forming an etch stop layer over the metal vertical electrode plates to a thickness of from about 100 to 1000 Å

;

the etch stop layer 100 being formed of SiN or Si_xO_yN_z;

forming an upper low-k dielectric material layer over the etch stop layer;

the upper low-k dielectric material layer having a dielectric constant of less than about 3.0; and

forming respective via structures within the etch stop layer and the upper low-k dielectric material layer in electrical communication with the respective metal vertical electrode plates.

21. The method of claim 1, including the steps of:

forming an etch stop layer over the metal vertical electrode plates to a thickness of from about 300 to 600 Å

;

the etch stop layer being formed of SiN;

forming an upper low-k dielectric material layer over the etch stop layer;

the upper low-k dielectric material layer having a dielectric constant of less than about 3.0; and

forming respective via structures within the etch stop layer and the upper low-k dielectric material layer in electrical communication with the respective metal vertical electrode plates.

22. A method of forming a capacitor, comprising the steps of:

providing a substrate having a lower low-k dielectric layer formed thereover;

the lower low-k dielectric layer having a dielectric constant of less than about 3.0;

forming copper vertical electrode plates within the lower low-k dielectric layer such that adjacent copper vertical electrode plates have lower low-k dielectric layer portions therebetween; and

replacing the lower low-k dielectric layer portions between the adjacent copper vertical electrode plates with high-k dielectric material trench portions;

the high-k dielectric material trench portions having a dielectric constant of greater than about 3.0.

23. The method of claim 22, wherein the lower low-k dielectric layer has a thickness of from about 2000 to 50,000 Å

.

24. The method of claim 22, wherein the lower low-k dielectric layer has a thickness of from about 5000 to 10,000 Å

.

25. The method of claim 22, wherein the lower low-k dielectric layer is comprised of TEOS, FTEOS, Coral™

, Black Diamond™

or an organic material.

26. The method of claim 22, wherein the lower low-k dielectric layer is comprised of an organic material.

27. The method of claim 22, wherein the high-k dielectric material trench portions are comprised of SiN, Ta_xO_y, Hf_xO_y, Ti_xO_y, Al₂O₃, Ta_xAl_yO_z, Ti_xAl_yO_z, SiO₂, Ta_xN_yO_z, Ti_xN_yO_z or a non-conductive oxidized refractory metal.

28. The method of claim 22, wherein the high-k dielectric material trench portions are comprised of a low leakage and high breakdown material.

29. The method of claim 22, wherein the high-k dielectric material trench portions have a dielectric constant of from about 7.0 to 50.0.

30. The method of claim 22, including the step of lining the copper vertical electrode plates with respective metal barrier layers.

31. The method of claim 22, including the step of lining the copper vertical electrode plates with respective metal barrier layers comprised of Ta or TaN.

32. The method of claim 22, including the step of lining the copper vertical electrode plates with respective metal barrier layers comprised of Ta/TaN.

33. The method of claim 22, including the steps of:

forming an upper low-k dielectric material layer over the copper vertical electrode plates;

the upper low-k dielectric material layer having a dielectric constant of less than about 3.0; and

forming respective via structures within the upper low-k dielectric material layer in electrical communication with the respective copper vertical electrode plates.

34. The method of claim 22, including the steps of:

forming an upper low-k dielectric material layer over the copper vertical electrode plates;

the upper low-k dielectric material layer having a dielectric constant of less than about 3.0; and

forming respective lined via structures within the upper low-k dielectric material layer in electrical communication with the respective copper vertical electrode plates.

35. The method of claim 22, including the steps of:

forming an upper low-k dielectric material layer over the copper vertical electrode plates to a thickness of from about 2000 to 50,000 Å

;

the upper low-k dielectric material layer having a dielectric constant of less than about 3.0; and

forming respective via structures within the upper low-k dielectric material layer in electrical communication with the respective copper vertical electrode plates;

the via structures being comprised of copper or tungsten.

36. The method of claim 22, including the steps of:

forming an upper low-k dielectric material layer over the copper vertical electrode plates to a thickness of from about 5000 to 10,000 Å

;

the upper low-k dielectric material layer having a dielectric constant of less than about 3.0; and

forming respective via structures within the upper low-k dielectric material layer in electrical communication with the respective copper vertical electrode plates;

the via structures being comprised of copper.

37. The method of claim 22, including the steps of:

forming an etch stop layer over the copper vertical electrode plates;

forming an upper low-k dielectric material layer over the etch stop layer;

the upper low-k dielectric material layer having a dielectric constant of less than about 3.0; and

forming respective via structures within the etch stop layer and the upper low-k dielectric material layer in electrical communication with the respective copper vertical electrode plates.

38. The method of claim 22, including the steps of:

forming an etch stop layer over the copper vertical electrode plates to a thickness of from about 100 to 1000 Å

;

the etch stop layer 100 being formed of SiN or Si_xO_yN_z;

forming an upper low-k dielectric material layer over the etch stop layer;

the upper low-k dielectric material layer having a dielectric constant of less than about 3.0; and

forming respective via structures within the etch stop layer and the upper low-k dielectric material layer in electrical communication with the respective copper vertical electrode plates.

39. The method of claim 22, including the steps of:

forming an etch stop layer over the copper vertical electrode plates to a thickness of from about 300 to 600 Å

;

the etch stop layer being formed of SiN;

forming an upper low-k dielectric material layer over the etch stop layer;

the upper low-k dielectric material layer having a dielectric constant of less than about 3.0; and

forming respective via structures within the etch stop layer and the upper low-k dielectric material layer in electrical communication with the respective copper vertical electrode plates.

40. A method of forming a capacitor, comprising the steps of:

providing a semiconductor wafer having a lower low-k dielectric layer formed thereover;

the lower low-k dielectric layer having a dielectric constant of less than about 3.0 and a thickness of from about 2000 to 50,000 Å

;

forming metal vertical electrode plates within the lower low-k dielectric layer such that adjacent metal vertical electrode plates have lower low-k dielectric layer portions therebetween;

the metal vertical electrode plates being comprised of copper or tungsten; and

replacing the lower low-k dielectric layer portions between the adjacent metal vertical electrode plates with high-k dielectric material trench portions;

the high-k dielectric material trench portions having a dielectric constant of greater than about 3.0 and are comprised of a non-conductive oxidized refractory metal.

41. The method of claim 40, wherein the lower low-k dielectric layer has a thickness of from about 5000 to 10,000 Å

.

42. The method of claim 40, wherein the lower low-k dielectric layer is comprised of TEOS, FTEOS, Coral™

, Black Diamond®

or an organic material.

43. The method of claim 40, wherein the lower low-k dielectric layer is comprised of an organic material.

44. The method of claim 40, wherein the high-k dielectric material trench portions are comprised of SiN, Ta_x,O_y, Hf_xO_y, Ti_xO_y, Al₂O₃, Ta_xAl_yO_z, Ti_xAl_yO_z, SiO₂, Ta_xN_yO_z or Ti_xN_yO_z.

45. The method of claim 40, wherein the high-k dielectric material trench portions have a dielectric constant of from about 7.0 to 50.0.

46. The method of claim 40, wherein the metal vertical electrode plates are comprised of copper.

47. The method of claim 40, including the step of lining the metal vertical electrode plates with respective metal barrier layers.

48. The method of claim 40, including the step of lining the metal vertical electrode plates with respective metal barrier layers comprised of Ta or TaN.

49. The method of claim 40, including the step of lining the metal vertical electrode plates with respective metal barrier layers comprised of Ta/TaN.

50. The method of claim 40, including the steps of:

forming an upper low-k dielectric material layer over the metal vertical electrode plates;

the upper low-k dielectric material layer having a dielectric constant of less than about 3.0; and

forming respective via structures within the upper low-k dielectric material layer in electrical communication with the respective metal vertical electrode plates.

51. The method of claim 40, including the steps of:

forming an upper low-k dielectric material layer over the metal vertical electrode plates;

the upper low-k dielectric material layer having a dielectric constant of less than about 3.0; and

forming respective lined via structures within the upper low-k dielectric material layer in electrical communication with the respective metal vertical electrode plates.

52. The method of claim 40, including the steps of:

forming an upper low-k dielectric material layer over the metal vertical electrode plates to a thickness of from about 2000 to 50,000 Å

;

the upper low-k dielectric material layer having a dielectric constant of less than about 3.0; and

forming respective via structures within the upper low-k dielectric material layer in electrical communication with the respective metal vertical electrode plates;

the via structures being comprised of copper or tungsten.

53. The method of claim 40, including the steps of:

forming an upper low-k dielectric material layer over the metal vertical electrode plates to a thickness of from about 5000 to 10,000 Å

;

the upper low-k dielectric material layer having a dielectric constant of less than about 3.0; and

forming respective via structures within the upper low-k dielectric material layer in electrical communication with the respective metal vertical electrode plates;

the via structures being comprised of copper.

54. The method of claim 40, including the steps of:

forming an etch stop layer over the metal vertical electrode plates;

forming an upper low-k dielectric material layer over the etch stop layer;

the upper low-k dielectric material layer having a dielectric constant of less than about 3.0; and

forming respective via structures within the etch stop layer and the upper low-k dielectric material layer in electrical communication with the respective metal vertical electrode plates.

55. The method of claim 40, including the steps of:

forming an etch stop layer over the metal vertical electrode plates to a thickness of from about 100 to 1000 Å

;

the etch stop layer 100 being formed of SiN or Si_xO_yN_z;

forming an upper low-k dielectric material layer over the etch stop layer;

the upper low-k dielectric material layer having a dielectric constant of less than about 3.0; and

forming respective via structures within the etch stop layer and the upper low-k dielectric material layer in electrical communication with the respective metal vertical electrode plates.

56. The method of claim 40, including the steps of:

forming an etch stop layer over the metal vertical electrode plates to a thickness of from about 300 to 600 Å

;

the etch stop layer being formed of SiN;

forming an upper low-k dielectric material layer over the etch stop layer;

the upper low-k dielectric material layer having a dielectric constant of less than about 3.0; and

forming respective via structures within the etch stop layer and the upper low-k dielectric material layer in electrical communication with the respective metal vertical electrode plates.