Electrically Programmable Three-Dimensional Memory Structures and Cells

• US 20050087817A1
• Filed: 01/12/2005
• Published: 04/28/2005
• Est. Priority Date: 04/08/2002
• Status: Abandoned Application

• Current Assignee: Guobiao Zhang
• Original Assignee: Guobiao Zhang
• Inventors: Zhang, Guobiao
• Application Number:
  US10/905,609
• Publication Number:
  US 20050087817A1
• Time in Patent Office: Days
• US Class Current: 257/390
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/74 Thyristor-type devices, e.g. having four-zone regenerative action two-terminal thyristors H01L29/87
• CPC Class Codes: H01L 29/76 Unipolar devices , e.g. field effect transistors

Abstract

The present invention makes various improvements to the electrically programmable three-dimensional memory (EP-3DM), including its structure and cell design. Redundancy can be employed to improve its yield.

Claims

1. An electrically programmable three-dimensional memory (EP-3DM), comprising:

a substrate circuit, said substrate circuit comprising a plurality of active devices and an interconnect system connecting said active devices, said substrate circuit further comprising an address-decoder;

at least an EP-3DM level stacked on top of said substrate circuit and connected with said substrate circuit through a plurality of inter-level connecting vias, said EP-3DM level comprising a plurality of address-selection lines and EP-3DM cells, said address-decoder decoding address for at least a portion of said EP-3DM level.

2. The EP-3DM according to claim 1, wherein

said address-selection lines in said EP-3DM level comprises poly-crystalline semiconductor materials;

and

said interconnect system of said substrate circuit is made of refractory conductor and thermally-stable dielectric.

3. The EP-3DM according to claim 1, further comprising a shielding layer between said substrate circuit and at least a portion of said EP-3DM level.

4. The EP-3DM according to claim 1, further comprising:

at least an interconnect gap between two adjacent address-selection lines on said EP-3DM level; and

at least an embedded wire, said embedded wire passing through said EP-3DM level in said interconnect gap.

5. The EP-3DM according to claim 1, further comprising at least a routing level in said interconnect system of said substrate circuit, said routing level providing electrical connection between said EP-3DM level and said substrate circuit, at least a portion of said address-decoder located under said EP-3DM level.

6. The EP-3DM according to claim 1, wherein

at least an address-selection line in said EP-3DM level is a composite line, said composite line comprising a highly-conductive layer and a lightly-doped layer, said lightly-doped layer being located at the bottom of said composite line;

and

said EP-3DM further comprises a via and an inverted-U link, said via being located near one end of said composite line and said inverted-U link having an inverted-U shape, said via being connected with said composite line through said inverted-U link by making contacts to said highly-conductive layer on top and/or on sidewalls.

7. An electrically programmable three-dimensional memory (EP-3DM) cell, comprising:

a first electrode;

a second electrode; and

a 3D-ROM layer between said first and second electrodes, said 3D-ROM layer further comprising a quasi-conductive layer and an antifuse layer, said quasi-conductive layer having a lower resistance when the current flows in one direction than when the current flows in the opposite direction, said antifuse layer having a high resistance when un-programmed and a low resistance when programmed.

8. The EP-3DM cell according to claim 7, wherein

at least one of said first and second electrodes further comprises a semiconductor layer and a metallic layer, said semiconductor layer comprising doped semiconductor materials and said metallic layer comprising metallic materials.

9. The EP-3DM cell according to claim 7, wherein at least one of said first and second electrodes further comprises a semiconductor layer, said semiconductor layer being doped by metallic ions.

10. The EP-3DM cell according to claim 7, wherein said 3D-ROM layer is a polarized layer comprising at least two sub-layers with different base materials.

11. The EP-3DM cell according to claim 7, wherein said 3D-ROM layer has a polarized structure, the interface between said 3D-ROM layer and said first electrode being different from the interface between said 3D-ROM layer and said second electrode.

12. The EP-3DM cell according to claim 7, wherein said 3D-ROM layer comprises a large-bandgap semiconductor material, whereby said EP-3DM cell supports high-temperature operation.

13. The EP-3DM cell according to claim 7, wherein said 3D-ROM layer comprises a micro-crystalline semiconductor material.

14. The EP-3DM cell according to claim 7 being a quasi-seamless or seamless cell, wherein the interfaces between at least a portion of said 3D-ROM layer and said first electrode and between said portion of said 3D-ROM layer and said second electrode not exposed to any substantial material-removal processing step.

15. The EP-3DM cell according to claim 14, wherein said portion of said 3D-ROM layer is said antifuse layer.

16. The EP-3DM cell according to claim 14, wherein said portion of said 3D-ROM layer is said quasi-conductive layer.

17. An electrically programmable three-dimensional memory (EP-3DM), comprising:

a substrate circuit, said substrate circuit comprising an embedded ROM (eROM) and a plurality of multiplexors;

at least an electrically programmable three-dimensional memory (EP-3DM) level stacked on said substrate circuit, said EP-3DM level comprising at least a defective structure selected from a defective EP-3DM cell, a defective word line and a defective bit line;

a plurality of inter-level connecting vias, said inter-level connecting vias connecting said EP-3DM level with said substrate circuit;

wherein, the output for said EP-3DM is selected from said EP-3DM level and said eROM by said multiplexors.

18. The EP-3DM according to claim 17, wherein said eROM stores the row address, column address and correctional bit for said defective EP-3DM cell.

19. The EP-3DM according to claim 17, wherein said eROM stores the row address and correctional bits for all EP-3DM cells on said defective word line.

20. The EP-3DM according to claim 17, wherein said eROM stores the column address and correctional bits for all EP-3DM cells on said defective bit line.