High dielectric constant metal oxide gate dielectrics

• US 20050087820A1
• Filed: 08/22/2003
• Published: 04/28/2005
• Est. Priority Date: 12/15/1998
• Status: Active Grant

• Current Assignee: Brian S. Doyle, Chunlin Liang, David B. Fraser, Gang Bai, Peng Cheng
• Original Assignee: Brian S. Doyle, Chunlin Liang, David B. Fraser, Gang Bai, Peng Cheng
• Inventors: Doyle, Brian S., Bai, Gang, Cheng, Peng, Liang, Chunlin, Fraser, David B.
• Granted Patent: US 6,998,357 B2
• Time in Patent Office: Days
• US Class Current: 257/410
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 21/28229 by deposition of a layer, e.g. metal, metal compound or poysilicon, followed by transformation thereof into an insulating layer
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence

Abstract

A method of forming a dielectric layer suitable for use as the gate dielectric layer of a metal-oxide-semiconductor field effect transistor (MOSFET) includes oxidizing the surface of a silicon substrate, forming a metal layer over the oxidized surface, and reacting the metal with the oxidized surface to form a substantially intrinsic layer of silicon superjacent the substrate, wherein at least a portion of the silicon layer may be an epitaxial silicon layer, and a metal oxide layer superjacent the silicon layer. In a further aspect of the present invention, an integrated circuit includes a plurality of MOSFETs, wherein various ones of the plurality of transistors have metal oxide gate dielectric layers and substantially intrinsic silicon layers subjacent the metal oxide dielectric layers.

Claims

1. A field effect transistor (FET), comprising:

a metal oxide gate insulator disposed over a substantially intrinsic layer of silicon which overlies a substrate.

2. The FET of claim 1, wherein the metal oxide comprises an oxide of hafnium.

3. The FET of claim 1, wherein the metal oxide comprises an oxide of zirconium.

4. The FET of claim 1, wherein the metal oxide is an oxide of a rare earth element that has a higher heat of formation than silicon dioxide.

5. The FET of claim 1, wherein the substantially intrinsic layer of silicon is an epitaxial layer.

6. The FET of claim 4, further comprising a gate electrode overlying the metal oxide layer;

and source/drain terminals disposed in the substrate substantially adjacent the gate electrode.

7. The FET of claim 5, wherein the epitaxial layer has a thickness in the range of approximately 10 angstroms to 20 angstroms.

8. A method of forming a dielectric layer, comprising:

forming an oxide layer on a surface of a substrate;

forming a metal layer over the oxide layer;

forming a capping layer over the metal layer; and

reacting the metal layer with the oxide layer.

9. The method of claim 8, wherein the substrate comprises a silicon wafer, and the oxide layer is an oxide of silicon.

10. The method of claim 8, wherein forming the metal layer comprises depositing a layer of a metal which does not react with silicon to form a silicide.

11. The method of claim 8, further comprising removing the capping layer.

12. The method of claim 8, wherein the capping layer comprises titanium nitride, and further comprising removing the capping layer by a selective wet etch;

and further comprising removing unreacted metal from a surface of the metal oxide layer.

13. A method of forming a dielectric layer, comprising:

forming an oxide layer on a surface of a substrate;

forming a metal layer over the oxide layer; and

reacting at least a first portion of the metal layer with the oxide layer.

14. The method of claim 13, further comprising reacting a second portion of the metal layer with an oxidizing ambient.

15. The method of claim 13, wherein reacting at least a first portion of the metal layer with the oxide layer comprises heating to a temperature greater than approximately 600°

C.

16. A method of forming a field effect transistor, comprising:

growing a silicon dioxide layer on a surface of a silicon wafer;

depositing a metal layer superjacent the silicon dioxide layer;

depositing a capping layer superjacent the metal layer;

converting the silicon dioxide layer and the metal layer to an epitaxial silicon layer and a metal oxide layer;

removing the capping layer;

forming a gate electrode over the metal oxide; and

forming source/drain terminals substantially adjacent the gate electrode.

17. The method of claim 16, wherein forming the metal layer comprises depositing a metal;

and the metal is selected from the group consisting of hafnium and zirconium.

18. The method of claim 16, wherein forming the capping layer comprises depositing a titanium nitride layer.

19. The method of claim 18, wherein depositing comprises a physical vapor deposition.

20. The method of claim 16, wherein converting the silicon dioxide layer and the metal layer to an epitaxial silicon layer and a metal oxide layer comprises heating the wafer.

21. The method of claim 16, wherein removing the capping layer comprises a selective wet etch.

22. A method of forming a field effect transistor, comprising:

growing a silicon dioxide layer on a surface of a silicon wafer;

depositing a metal layer superjacent the silicon dioxide layer;

converting the silicon dioxide layer and the metal layer to an epitaxial silicon layer and a metal oxide layer;

forming a gate electrode over the metal oxide; and

forming source/drain terminals substantially adjacent the gate electrode.

23. The method of claim 22, wherein forming the metal layer comprises depositing a metal;

and the metal is selected from the group consisting of hafnium and zirconium.

24. The method of claim 23, wherein depositing comprises a physical vapor deposition.

25. The method of claim 22, wherein converting the silicon dioxide layer and the metal layer to an epitaxial silicon layer and a metal oxide layer comprises heating the wafer in a low pressure reaction chamber.

26. The method the claim 25, wherein the reaction chamber is the same reaction chamber in which the metal layer is formed.