Method for forming a bump, semiconductor device and method of fabricating same, semiconductor chip, circuit board, and electronic instrument

• US 20050087863A1
• Filed: 12/10/2004
• Published: 04/28/2005
• Est. Priority Date: 09/04/2000
• Status: Active Grant

• Current Assignee: 138 East LCD Advancements Limited (Vector Capital Corporation)
• Original Assignee: Akira Makabe, Fumiaki Matsushima, Tsutomu Ota
• Inventors: Matsushima, Fumiaki, Ota, Tsutomu, Makabe, Akira
• Granted Patent: US 7,355,280 B2
• Time in Patent Office: Days
• US Class Current: 257/712
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05164 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/11462 Electroplating
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/11822 by dipping, e.g. in a solder bath
• CPC Class Codes: H01L 2224/11849 Reflowing
• CPC Class Codes: H01L 2224/11901 with repetition of the same manufacturing step
• CPC Class Codes: H01L 2224/13012 in top view
• CPC Class Codes: H01L 2224/13078 being disposed next to each other, e.g. side-to-side arrangements
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/13083 Three-layer arrangements
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/1411 : the bump connectors being bonded to at least one common bonding area
• CPC Class Codes: H01L 2224/274 : by blanket deposition of the material of the layer connector
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01061 : Promethium [Pm]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA

Abstract

A method for forming a bump includes the steps of forming a resist layer so that a through-hole formed therein is located on a pad; and forming a metal layer to be electrically connected to the pad conforming to the shape of the through-hole. The metal layer is formed so as to have a shape in which is formed a region for receiving a soldering or brazing material.

Claims

1. A semiconductor device comprising:

a semiconductor chip;

a plurality of pads formed on the semiconductor chip; and

a plurality of metal layers and a plurality of leads;

wherein the plurality of metal layers and the plurality of leads are bonded through a soldering or brazing material, each of the metal layers are formed on each of the plurality of pads of the semiconductor chip, and each of the metal layers have a shape in which is formed a region for receiving the soldering or brazing material; and

the soldering or brazing material, when melted, is allowed to flow into a region of each of the metal layers for receiving the soldering or brazing material so as not to spread onto an adjacent pad of the plurality of pads.

2. A semiconductor chip comprising:

a plurality of pads; and

a metal layer disposed on each of the pads which is formed to have a shape in which is formed a region for receiving a soldering or brazing material.

3. The semiconductor chip according to claim 2, wherein at least one depression is formed in a side of the metal layer.

4. The semiconductor chip according to claim 2, wherein a depression which is provided in the direction of the height of the metal layer is formed at the center of the metal layer.

5. The semiconductor chip according to claim 2, wherein two or more metal layers are formed on one of the pads.

6. A semiconductor device comprising:

a semiconductor chip having a plurality of pads;

a metal layer disposed on each of the pads, the metal layer formed to have a shape in which is formed a region for receiving a soldering or brazing material; and

a plurality of leads;

wherein the metal layer is bonded to one of the leads through the soldering or brazing material, and part of the soldering or brazing material is put in the region for receiving the soldering or brazing material.

7. The semiconductor device according to claim 6, wherein at least one depression is formed in a side of the metal layer;

and

the soldering or brazing material is put in the depression.

8. The semiconductor device according to claim 6, wherein a depression which is provided in the direction of the height of the metal layer is formed at the center of the metal layer;

and

the soldering or brazing material is put in the depression.

9. The semiconductor device according to claim 6, wherein two or more of the metal layers are formed on one of the pads;

and

the soldering or brazing material is put in a region formed between adjacent metal layers of the two or more metal layers on one of the pads.

10. A circuit board on which is mounted the semiconductor device according to claim 6.

11. An electronic instrument comprising the semiconductor device according to claim 6.