Logic device having vertically extending metal-insulator-metal capacitor between interconnect layers and method of fabricating the same

• US 20050087879A1
• Filed: 10/20/2004
• Published: 04/28/2005
• Est. Priority Date: 10/28/2003
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Won, Seok-Jun, Kwon, Dae-Jin, Jeong, Yong-Kuk, Kim, Weon-Hong, Song, Min-Woo
• Granted Patent: US 7,476,922 B2
• Time in Patent Office: Days
• US Class Current: 257/758
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers

Abstract

A logic device having a vertically extending MIM capacitor between interconnect layers includes a semiconductor substrate. A lower interconnect layer is located over the semiconductor substrate, and an upper interconnect layer is located over the lower interconnect layer. A U-shaped lower metal plate is interposed between the lower interconnect layer and the upper interconnect layer. The U-shaped lower metal plate directly contacts the lower interconnect layer. The capacitor dielectric layer covers the inner surface of the lower metal plate. Further, the capacitor dielectric layer has an extension portion interposed between the brim of the lower metal plate and the upper interconnect layer. An upper metal plate covers the inner surface of the capacitor dielectric layer. The upper metal plate is in contact with the upper interconnect layer and is confined by the capacitor dielectric layer.

Claims

1. A logic device comprising:

a lower interconnect layer located over a semiconductor substrate;

an upper interconnect layer located over the lower interconnect layer;

a U-shaped lower metal plate interposed between the lower interconnect layer and the upper interconnect layer, and being in contact with the lower interconnect layer;

a capacitor dielectric layer covering the inner surface of the lower metal plate, and having an extension portion interposed between the brim of the lower metal plate and the upper interconnect layer; and

an upper metal plate covering the inner surface of the capacitor dielectric layer, contacting the upper interconnect layer, and being confined by the capacitor dielectric layer.

2. The logic device according to claim 1, further comprising:

a second lower interconnect layer located at the same level as the first lower interconnect layer;

a second upper interconnect layer located at the same level as the first upper interconnect layer; and

a via plug for electrically connecting the second lower interconnect layer and the second upper interconnect layer.

3. The logic device according to claim 2, further comprising an interlayer insulating layer interposed between the second lower interconnect layer and the second upper interconnect layer, and extending to cover the outer side walls of the lower metal plate and the outer side walls of the extension portion of the capacitor dielectric layer.

4. The logic device according to claim 3, wherein the capacitor dielectric layer extends to be interposed between the interlayer insulating layer and the first upper interconnect layer, and to be interposed between the interlayer insulating layer and the second upper interconnect layer.

5. The logic device according to claim 3, wherein the second lower interconnect layer is electrically connected to the first lower interconnect layer, and the second upper interconnect layer is electrically insulated from the first upper interconnect layer.

6. The logic device according to claim 3, wherein the extension portion of the capacitor dielectric layer is from 200 Å

to 1000 Å

in height.

7. A logic device comprising:

a semiconductor substrate;

a lower interconnect layer located over the semiconductor substrate;

an upper interconnect layer located over the lower interconnect layer;

a plurality of U-shaped lower metal plates interposed between the lower interconnect layer and the upper interconnect layer, and spaced from each other being in contact with the lower interconnect layer;

capacitor dielectric layers covering the inner surface of the respective lower metal plates and having extension portions interposed between the brim of the lower metal plates and the upper interconnect layer; and

upper metal plates covering the inner surface of the respective capacitor dielectric layers, wherein each of the upper metal plates is in contact with the upper interconnect layer and is confined by the capacitor dielectric layer.

8. The logic device according to claim 7, further comprising:

a second lower interconnect layer located at the same level as the first lower interconnect layer;

a second upper interconnect layer located at the same level as the first upper interconnect layer; and

a via plug for electrically connecting the second lower interconnect layer and the second upper interconnect layer.

9. The logic device according to claim 8, further comprising an interlayer insulating layer, surrounding the via plug, interposed between the second upper interconnect layer and the second lower interconnect layer, wherein the interlayer insulating layer extends to cover the outer side walls of the lower metal plates and the outer side walls of the extension portions of the capacitor dielectric layers.

10. The logic device according to claim 9, wherein the capacitor dielectric layers extend to be interposed between the interlayer insulating layer and the first upper interconnect layer, and are interposed between the interlayer insulating layer and the second upper interconnect layer.

11. The logic device according to claim 9, wherein the second lower interconnect layer is electrically connected to the first lower interconnect layer, and the second upper interconnect layer is electrically insulated from the first upper interconnect layer.

12. The logic device according to claim 9, wherein the extension portions of the capacitor dielectric layers are 200 Å

to 1000 Å

in height.

13. The logic device according to claim 9, further comprising a via diffusion barrier layer interposed between the interlayer insulating layer and the via plug, and interposed between the second lower interconnect layer and the via plug.

14. The logic device according to claim 13, wherein the upper metal plate is at least one layer selected from the group including Ti, TiN, Ta, TaN, Ru, and WN layers.

15. The logic device according to claim 14, wherein the capacitor dielectric layer is at least one layer selected from the group including Ta₂O₅, Al₂O₃, HfO₂, ZrO₂, La₂O₃, TiO₂, ST and BST layers.

16. The logic device according to claim 15, wherein the via diffusion barrier layer is at least one layer selected from the group including Ti, TiN, Ta, TaN, Ru, and WN layers.

17. The logic device according to claim 16, wherein the via diffusion barrier layer is a material layer different from the upper metal plate layer.

18. A method of fabricating a logic device comprising the steps of:

preparing a semiconductor substrate having a lower insulating layer;

forming a first lower interconnect layer and a second lower interconnect layer over the semiconductor substrate;

forming an interlayer insulating layer over the semiconductor substrate having the first lower interconnect layer and the second lower interconnect layer formed thereon;

patterning the interlayer insulating layer using photolithography and etching processes, to form at least one capacitor hole for exposing the top surface of the first lower interconnect layer;

forming a lower metal plate covering the top surface of the exposed first lower interconnect layer and the side walls of the at least one capacitor hole, and being recessed inside the capacitor hole;

forming conformably a capacitor dielectric layer, an upper metal plate layer, and a capacitor plug layer on the overall surface of the semiconductor substrate having the lower metal plate formed thereon;

removing the capacitor plug layer and the upper metal plate layer such that the top surface of the capacitor dielectric layer is exposed, to form an upper metal plate and a capacitor plug, which are confined by the capacitor dielectric layer;

patterning the exposed dielectric layer and the interlayer insulating layer after the upper metal plate is formed, so as to form a via hole for exposing the second lower interconnect layer;

forming a via plug for burying the via hole; and

forming a first upper interconnect layer being in contact with the upper metal plate, and a second upper interconnect layer being in contact with the via plug on the semiconductor substrate having the via plug formed thereon.

19. The method according to claim 18, wherein the step of forming the lower metal plate comprises the steps of:

forming conformably a lower metal plate layer on the overall surface of the semiconductor substrate having the at least one capacitor hole formed thereon;

forming an etch sacrificial layer on the overall surface of the semiconductor substrate having the lower metal plate layer formed thereon for filling the at least one capacitor hole;

forming a recessed etch sacrificial layer, which is confined inside the at least one capacitor hole, by overall-etching the etch sacrificial layer;

etching the lower metal plate layer using the recessed etch sacrificial layer as an etch mask, to recess the lower metal plate layer inside the at least one capacitor hole; and

removing the recessed etch sacrificial layer.

20. The method according to claim 19, wherein the step of forming the via plug comprises the steps of:

forming a via diffusion barrier layer and a via plug layer on the semiconductor substrate having the via hole formed thereon; and

sequentially removing the via diffusion barrier layer and the via plug layer until the top surface of the interlayer insulating layer is exposed.

21. The method according to claim 19, wherein the step of forming the upper interconnect layer and the second upper interconnect layer comprises the steps of:

forming an upper conductive layer on the semiconductor substrate having the via plug formed thereon; and

patterning the upper conductive layer.

22. The method according to claim 21, further comprising the steps of:

forming an upper insulating layer on the semiconductor substrate having the via plug formed thereon before forming the upper conductive layer; and

patterning the upper insulating layer using photolithography and etching processes, so as to form a first groove for exposing the upper metal plate and a second groove for exposing the via plug,

wherein the upper conductive layer is patterned by using CMP technology.

23. The method according to claim 21, wherein the removal of the capacitor plug layer and the upper metal plate layer is performed by CMP technology.

24. The method according to claim 19, further comprising a step of:

removing sequentially the exposed capacitor dielectric layer after exposing the top surface of the capacitor dielectric layer, the upper metal plate, and the capacitor plug until the top surface of the interlayer insulating layer is exposed, so as to form an upper metal plate confined inside the capacitor hole and a capacitor plug confined inside the capacitor hole.

25. The method according to claim 19, wherein the lower metal plate is recessed a thickness of 200 Å

to 1000 Å

compared to the interlayer insulating layer.

26. A method of fabricating a logic device comprising the steps of:

preparing a semiconductor substrate having a first lower interconnect layer and a second lower interconnect layer formed thereon;

forming an interlayer insulating layer on the semiconductor substrate having the first lower interconnect layer and the second lower interconnect layer formed thereon;

patterning the interlayer insulating layer using photolithography and etching processes, to form at least one capacitor hole for exposing the top surface of the first lower interconnect layer;

forming a lower metal plate, recessed inside the capacitor hole, covering the top surface of the exposed first lower interconnect layer and the side walls of the at least one capacitor hole;

forming conformably a capacitor dielectric layer, an upper metal plate layer, and a capacitor plug layer on the overall surface of the semiconductor substrate having the lower metal plate formed thereon;

removing the capacitor plug layer and the upper metal plate layer until the top surface of the dielectric layer is exposed, so as to form an upper metal plate and a capacitor plug confined by the capacitor dielectric layer;

forming an upper insulating layer over the semiconductor substrate having the upper metal plate formed thereon;

sequentially patterning the upper insulating layer, the exposed dielectric layer, and the interlayer insulating layer, to form a first groove for exposing the upper metal plate, a via hole for exposing the second lower interconnect layer, and a second groove intersecting over the via hole;

forming an upper conductive layer over the semiconductor substrate having the via hole and the grooves formed thereon; and

patterning the upper conductive layer using CMP technology, to form a first upper interconnect layer connected electrically to the upper metal plate and a second upper interconnect layer connected electrically to the second lower interconnect layer through the via hole.