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Isolation buffers with controlled equal time delays

  • US 20050088167A1
  • Filed: 10/23/2003
  • Published: 04/28/2005
  • Est. Priority Date: 10/23/2003
  • Status: Active Grant
First Claim
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1. An apparatus comprising:

  • a variable delay isolation buffer having a signal input, a variable delay control input, and an output; and

    a delay control circuit having an output providing the variable delay control input of the variable delay isolation buffer, the delay control circuit setting a delay control voltage potential at its output to control delay through the variable delay isolation buffer to substantially match delay through a time delay reference.

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