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System and apparatus for using test structures inside of a chip during the fabrication of the chip

  • US 20050090027A1
  • Filed: 08/25/2004
  • Published: 04/28/2005
  • Est. Priority Date: 08/25/2003
  • Status: Active Grant
First Claim
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1. A method for evaluating a fabrication of a semiconductor wafer, the method comprising:

  • locating one or more test structures in a die on the wafer, wherein each of the one or more test structures is activatable to exhibit electrical activity that is indicative of a quality metric of the fabrication sequence and/or of a particular fabrication step or sequence in the fabrication;

    subjecting the wafer to at least one of a plurality of fabrication processes that comprise the fabrication;

    activating the one or more test structure with a power signal and a test signal generated from within the die;

    measuring electrical activity generated from the at least one or more test structures in order to determine a performance parameter value of one or more test structures; and

    using a correlation between the particular fabrication step or sequence of the die and the performance parameter value of each of the one or more test structures to evaluate the fabrication.

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