Card manufacturing technique and resulting card

• US 20050090038A1
• Filed: 11/12/2004
• Published: 04/28/2005
• Est. Priority Date: 08/03/2001
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Robert F. Wallace
• Inventors: Wallace, Robert F.
• Granted Patent: US 7,169,640 B2
• Time in Patent Office: Days
• US Class Current: 438/106
• CPC Class Codes: G06K 19/077 Constructional details, e.g. mounting of circuits in the carrier
• CPC Class Codes: G06K 19/07732 the record carrier having a housing or construction similar to well-known portable memory devices, such as SD cards, USB or memory sticks housings for electrical equipment in general, see H05K5/02
• CPC Class Codes: G06K 19/07735 the record carrier comprising means for protecting against electrostatic discharge
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H05K 1/0256 Electrical insulation details, e.g. around high voltage areas
• CPC Class Codes: H05K 1/0259 Electrostatic discharge [ESD] protection
• CPC Class Codes: H05K 1/0268 for electrical inspection or testing
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 1/117 Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
• CPC Class Codes: H05K 2201/0919 Exposing inner circuit layers or metal planes at the side edge of the printed circuit board [PCB] or at the walls of large holes
• CPC Class Codes: H05K 2201/093 Layout of power planes, ground planes or power supply conductors, e.g. having special clearance holes therein
• CPC Class Codes: H05K 2201/09309 Core having two or more power planes; Capacitive laminate of two power planes
• CPC Class Codes: H05K 2201/0969 Apertured conductors
• CPC Class Codes: H05K 2203/175 Configurations of connections suitable for easy deletion, e.g. modifiable circuits or temporary conductors for electroplating; Processes for deleting connections
• CPC Class Codes: H05K 3/0052 Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
• CPC Class Codes: H05K 3/242 characterised by using temporary conductors on the printed circuit for electrically connecting areas which are to be electroplated

Abstract

A card manufacturing technique and the resulting card are provided. The card has a ground and/or power layer extending to the edges of a circuit board for electrostatic discharge protection but also has gaps at the edge of the ground and/or power layer to avoid short circuiting with conductive segments of another layer deformed when the card is trimmed during manufacture.

Claims

1. A circuit board having at least one peripheral edge comprising:

a first conductive layer having conductive segments at the edge of the circuit board;

a first insulative layer;

a second conductive layer separated from the first conductive layer by the first insulative layer, positioned below the first conductive layer, and extending to the edge of the circuit board, the second conductive layer having gaps at the edge of the circuit board, one or more of the gaps aligned with the conductive segments whereby any deformation of the conductive segments that extends over the edge to the plane of the second layer extends within the gaps and does not contact the second conductive layer.

2. The circuit board of claim 1 wherein the gaps are slots.

3. The circuit board of claim 1 wherein the gaps are notches.

4. The circuit board of claim 1 wherein the width of the gap is smaller away from the edge than it is at the edge of the circuit board.

5. The circuit board of claim 1 wherein the second conductive layer is the ground or power layer.

6. The circuit board of claim 1 further comprising a third conductive layer, the third conductive layer having gaps at the edge of the circuit board, the gaps aligned with the conductive segments whereby any deformation of the conductive segments that extends to the plane of the third layer extends within the gaps and does not contact the third conductive layer.

7. The circuit board of claim 6 wherein the third conductive layer is the ground or power layer.

19. The circuit board of claim 1 further comprising at least one integrated circuit including flash memory, circuit traces, and passive components.

8. A method of making a multi-layer circuit board:

forming a first conductive layer having conductive segments positioned along at least one edge of the circuit board;

forming an insulative layer below the first conductive layer

forming a second conductive layer below the first conductive layer and the insulative layer, said second conductive layer having gaps positioned along the at least one edge of the circuit board, at least one of said gaps larger than said conductive segments and aligned with said conductive segments;

trimming the circuit board and the conductive segments such that any deformation of the segments extends into the gaps and does not make contact with the second conductive layer.

9. The method of claim 8 wherein the step of trimming the circuit board comprises the step of shearing the circuit board.

10. The method of claim 9 wherein the first conductive layer is sheared before the second conductive layer.

11. A circuit board having at least one edge comprising:

a power layer extending to the at least one edge;

a ground layer extending to the at least one edge; and

at least one additional layer having metallic segments at the at least one edge of the circuit board, the at least one additional layer separated from the ground or power layer by an insulating layer;

wherein portions of the ground or power layer positioned under the metallic segments at the at least one edge are slotted whereby any deformation of the metallic segments at said at least one edge does not contact the ground or power layer.

12. The circuit board of claim 11 wherein the metallic segments connect to a bus which is also trimmed from the circuit board.

13. The circuit board of claim 11 wherein the metallic segments are circuit traces.

14. The circuit board of claim 11 wherein the metallic segments are test leads.

15. A structure comprising:

a metallic layer comprising at least one bus, a first area, and segments connecting the at least one bus to the first area; and

a circuit board comprising;

at least one edge, wherein the first area of the metallic layer forms a first layer of the circuit board and wherein the segments connecting the bus to the first area are positioned at the at least one edge of the circuit board and extend over the at least one edge of the circuit board to the at least one bus;

an insulative layer below the metallic layer; and

a second conductive layer positioned below the metallic layer and the insulative layer and extending to the at least one edge, the second conductive layer having gaps at the at least one edge of the circuit board, whereby at least one of the gaps is aligned with at least one of the segments.

16. The structure of claim 15 whereby any deformation of the conductive segments that extends over the at least one edge to the plane of the second conductive layer extends within the gaps and does not contact the second conductive layer.

17. A method of making a memory storage device comprising a circuit board, a cover, and a junction between an edge of the circuit board and the cover comprising:

forming a first metallic layer comprising a first area, a bus, and a plurality of segments connecting the first area to the bus at the edge of the circuit board, the first area positioned within the circuit board, the bus positioned without the circuit board;

forming an insulating layer below the first area of the first metallic layer;

forming a second metallic layer below the insulating layer and separated from the first metallic layer by the insulating layer, the second metallic layer extending to the edge of the circuit board and having a plurality of gaps at the edge of the circuit board positioned below the plurality of segments;

shearing the plurality of segments at the edge of the circuit board and removing the bus such that any deformation of the segments falls within the gaps of the second metallic layer.

18. The method of claim 17 further comprising placing the circuit board into the cover such that the edge of the circuit board and of the second metallic layer is at the junction between the cover and the circuit board.

20. The circuit board of 11 further comprising at least one integrated circuit including flash memory, circuit traces, and passive components.