High voltage N-LDMOS transistors having shallow trench isolation region
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Accused Products
Abstract
A method and structure is disclosed for a transistor having a gate, a channel region below the gate, a source region on one side of the channel region, a drain region on an opposite side of the channel region from the source region, a shallow trench isolation (STI) region in the substrate between the drain region and the channel region, and a drain extension below the STI region. The drain extension is positioned along a bottom of the STI region and along a portion of sides of the STI. Portions of the drain extension along the bottom of the STI may comprise different dopant implants than the portions of the drain extensions along the sides of the STI. Portions of the drain extensions along sides of the STI extend from the bottom of the STI to a position partially up the sides of the STI. The STI region is below a portion of the gate. The drain extension provides a conductive path between the drain region and the channel region around a lower perimeter of the STI. The drain region is positioned further from the gate than the source region.
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Citations
36 Claims
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1-13. -13. (canceled)
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14. A method of manufacturing a transistor comprising:
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forming a trench in a substrate;
implanting a drain extension through said trench into said substrate;
filling said trench with a shallow trench isolation (STI) material;
defining a channel region in said substrate on one side said STI material;
forming a source region in said substrate on an opposite side of said channel region from said STI material;
forming a drain region in said substrate on an opposite side of said STI material from said channel region; and
forming a gate above said channel region. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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21. A method of manufacturing a transistor comprising:
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forming a trench in a substrate;
partially filling said trench with a sacrificial material;
forming spacers in said trench above said sacrificial material;
removing said sacrificial material;
implanting a drain extension through said trench into exposed portions of said substrate, wherein said drain extension is implanted to regions of said substrate along sides and a bottom of said trench;
filling said trench with a shallow trench isolation (STI) material;
defining a channel region in said substrate on one side said STI material;
forming a source region in said substrate on an opposite side of said channel region from said STI material;
forming a drain region in said substrate on an opposite side of said STI material from said channel region; and
forming a gate above said channel region. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28)
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29. A transistor comprising:
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a gate on a substrate;
a channel region in said substrate below said gate;
a source region in said substrate on one side of said channel region, a drain region in said substrate on an opposite side of said channel region from said source region;
a shallow trench isolation (STI) region in said substrate between said drain region and said channel region, wherein said STI region comprises a trench in said substrate, sidewall spacers along walls of said trench, and an isolation material between said spacers filling said trench; and
a drain extension below said STI region. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36)
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Specification