Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format

• US 20050091434A1
• Filed: 11/23/2004
• Published: 04/28/2005
• Est. Priority Date: 12/17/1997
• Status: Active Grant

• Current Assignee: FG SRC LLC (Freeman Capital Partners LP)
• Original Assignee: SRC Computers, LLC
• Inventors: Huppenthal, Jon M., Burton, Lee A., Seeman, Thomas R.
• Granted Patent: US 7,421,524 B2
• Time in Patent Office: Days
• US Class Current: 710/305
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture

Abstract

A switch/network adapter port (“SNAP”) for clustered computers employing multi-adaptive processor (“MAP™”, a trademark of SRC Computers, Inc.) elements in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format to significantly enhance data transfer rates over that otherwise available through use of the standard peripheral component interconnect (“PCI”) bus. Particularly disclosed is a microprocessor based computer system utilizing either a DIMM or RIMM physical format processor element for the purpose of implementing a connection to an external switch, network, or other device. In a particular embodiment, connections may be provided to either the PCI, accelerated graphics port (“AGP”) or system maintenance (“SM”) bus for purposes of passing control information to the host microprocessor or other control chips. The field programmable gate array (“FPGA”) based processing elements have the capability to alter data passing through it to and from an external interconnect fabric or device.

Claims

1-36. -36. (canceled)

37. A processor element for a memory module bus of a computer system, said processor element comprising:

a field programmable gate array configurable to perform an identified algorithm on an operand provided thereto and operative to alter data provided thereto on said memory module bus; and

a data connection coupled to said field programmable gate array for providing said altered data to an external device coupled thereto.

38. The processor element of claim 37 further comprising:

a control connection coupled to said processor element for indicating to a processor of said computer system an arrival of data on said data connection from said external device.

39. The processor element of claim 38 wherein said control connection indicates said arrival of data to said processor by means of a peripheral bus.

40. The processor element of claim 39 wherein said peripheral bus comprises a PCI bus.

41. The processor element of claim 38 wherein said control connection indicates said arrival of data to said processor by means of a graphics bus.

42. The processor element of claim 41 wherein said graphics bus comprises an AGP bus.

43. The processor element of claim 38 wherein said control connection indicates said arrival of data to said processor by means of a system maintenance bus.

44. The processor element of claim 43 wherein said graphics bus comprises an SM bus.

45. The processor element of claim 37 wherein said memory module bus comprises a DIMM bus.

46. The processor element of claim 45 wherein said processor element comprises a DIMM physical format.

47. The processor element of claim 37 wherein said memory module bus comprises a RIMM bus.

48. The processor element of claim 47 wherein said processor element comprises a RIMM physical format.

49. The processor element of claim 37 wherein said external device comprises one of another computer system, switch or network.

50. The processor element of claim 37 wherein said processor of said computer system comprises a plurality of processors.

51. The processor element of claim 37 wherein said field programmable gate array is further operative to alter data provided thereto from said external device on said data connection and providing said altered data on said memory module bus.