Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
First Claim
1. An adaptive computing integrated circuit, comprising:
- a first plurality of heterogeneous computational elements, a first computational element of the first plurality of heterogeneous computational elements having a first fixed architecture and a second computational element of the first plurality of heterogeneous computational elements having a second fixed architecture;
a first interconnection network coupled to the first plurality of heterogeneous computational elements, the first interconnection network capable of configuring the first plurality of heterogeneous computational elements for a first functional mode of a plurality of functional modes in response to first configuration information, and the first interconnection network further capable of reconfiguring the first plurality of heterogeneous computational elements for a second functional mode of the plurality of functional modes in response to second configuration information;
a second plurality of heterogeneous computational elements, the second plurality of heterogeneous computational elements having a different set of computational elements than the first plurality of heterogeneous computational elements, a third computational element of the second plurality of heterogeneous computational elements having a third fixed architecture and a fourth computational element of the second plurality of heterogeneous computational elements having a fourth fixed architecture, wherein the first, second, third and fourth fixed architectures are each different fixed architectures;
a second interconnection network coupled to the second plurality of heterogeneous computational elements, the second interconnection network capable, independently from the configuration and reconfiguration of the first plurality of heterogeneous computational elements by the first interconnection network, of configuring the second plurality of heterogeneous computational elements for a third functional mode of the plurality of functional modes in response to third configuration information, and of reconfiguring the second plurality of heterogeneous computational elements for a fourth functional mode of the plurality of functional modes in response to fourth configuration information, wherein the first, second, third and fourth functional modes are each different functional modes; and
a third interconnection network coupled to the first plurality of heterogeneous computational elements and to the second plurality of heterogeneous computational elements, the third interconnection network capable of selectively routing data and control information to and from the first and second pluralities of heterogeneous computational elements.
3 Assignments
0 Petitions
Accused Products
Abstract
The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications.
-
Citations
93 Claims
-
1. An adaptive computing integrated circuit, comprising:
-
a first plurality of heterogeneous computational elements, a first computational element of the first plurality of heterogeneous computational elements having a first fixed architecture and a second computational element of the first plurality of heterogeneous computational elements having a second fixed architecture;
a first interconnection network coupled to the first plurality of heterogeneous computational elements, the first interconnection network capable of configuring the first plurality of heterogeneous computational elements for a first functional mode of a plurality of functional modes in response to first configuration information, and the first interconnection network further capable of reconfiguring the first plurality of heterogeneous computational elements for a second functional mode of the plurality of functional modes in response to second configuration information;
a second plurality of heterogeneous computational elements, the second plurality of heterogeneous computational elements having a different set of computational elements than the first plurality of heterogeneous computational elements, a third computational element of the second plurality of heterogeneous computational elements having a third fixed architecture and a fourth computational element of the second plurality of heterogeneous computational elements having a fourth fixed architecture, wherein the first, second, third and fourth fixed architectures are each different fixed architectures;
a second interconnection network coupled to the second plurality of heterogeneous computational elements, the second interconnection network capable, independently from the configuration and reconfiguration of the first plurality of heterogeneous computational elements by the first interconnection network, of configuring the second plurality of heterogeneous computational elements for a third functional mode of the plurality of functional modes in response to third configuration information, and of reconfiguring the second plurality of heterogeneous computational elements for a fourth functional mode of the plurality of functional modes in response to fourth configuration information, wherein the first, second, third and fourth functional modes are each different functional modes; and
a third interconnection network coupled to the first plurality of heterogeneous computational elements and to the second plurality of heterogeneous computational elements, the third interconnection network capable of selectively routing data and control information to and from the first and second pluralities of heterogeneous computational elements. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
-
-
18. A method for adaptive computing comprising:
-
in response to a first plurality of configuration information, configuring and reconfiguring through a first interconnection network a first plurality of heterogeneous computational elements for a first plurality of functional modes, the first plurality of heterogeneous computational elements forming a first reconfigurable architecture;
in response to a second plurality configuration information, independently configuring and reconfiguring through a second interconnection network a second plurality of heterogeneous computational elements for a second plurality of functional modes, the second plurality of heterogeneous computational elements forming a second reconfigurable architecture, wherein the second plurality of functional modes are different from the first plurality of functional modes and wherein the second reconfigurable architecture is different from the first reconfigurable architecture; and
reconfigurably routing, through a third interconnection network, data and control information to and from the first and second pluralities of heterogeneous computational elements. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
-
-
33. An adaptive computing integrated circuit, comprising:
-
a plurality of heterogeneous reconfigurable matrices comprising at least two distinct and different matrix architectures, each heterogeneous reconfigurable matrix of the plurality of heterogeneous reconfigurable matrices comprising a plurality of heterogeneous computation units, wherein each of the plurality of heterogeneous computation units are formed from a selected configuration, of a plurality of configurations, of a plurality of fixed computational elements, a first computational element of the plurality of fixed computational elements having a first fixed architecture and a second computational element of the plurality of fixed computational elements having a second fixed architecture, wherein the first fixed architecture is different from the second fixed architecture, and wherein each of the plurality of heterogeneous computation units is coupled to a corresponding first interconnect network and configurable and reconfigurable in response to a first plurality of configuration information for a corresponding plurality of functional modes; and
a second interconnection network coupled to the plurality of heterogeneous reconfigurable matrices, the second interconnection network capable of configuring and reconfiguring the plurality of heterogeneous reconfigurable matrices in response to a second plurality of configuration information for a corresponding plurality of operating modes. - View Dependent Claims (34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47)
-
-
48. An adaptive computing integrated circuit, comprising:
-
a first plurality of heterogeneous computational elements, a first computational element of the first plurality of heterogeneous computational elements having a first fixed architecture and a second computational element of the plurality of heterogeneous computational elements having a second fixed architecture;
a first interconnection network coupled to the first plurality of heterogeneous computational elements, the first interconnection network capable of configuring and reconfiguring the first plurality of heterogeneous computational elements for a first plurality of functional modes in response to a first plurality of configuration information;
a second plurality of heterogeneous computational elements, a third computational element of the second plurality of heterogeneous computational elements having a third fixed architecture and a fourth computational element of the second plurality of heterogeneous computational elements having a fourth fixed architecture, wherein the first, second, third and fourth fixed architectures are each different fixed architectures;
a second interconnection network coupled to the second plurality of heterogeneous computational elements, the second interconnection network capable of configuring and reconfiguring the second plurality of heterogeneous computational elements for a second plurality of functional modes in response to a second plurality of configuration information, wherein the first plurality of functional modes and the second plurality of functional modes are each different pluralities of functional modes;
a third interconnection network coupled to the first plurality of heterogeneous computational elements and to the second plurality of heterogeneous computational elements, the third interconnection network capable of selectively routing data and control information to and from the first and second pluralities of heterogeneous computational elements;
a third plurality of heterogeneous computational elements coupled to the third interconnection network, the third plurality of heterogeneous computational elements configured for a controller operating mode, the controller operating mode comprising functions for directing configuration and reconfiguration of the first and second pluralities of heterogeneous computational elements, for selecting the first and second pluralities of configuration information from a singular bit stream comprising data commingled with the first and second pluralities of configuration information, and for scheduling the configuration and reconfiguration of the first and second pluralities of heterogeneous computational elements with corresponding data; and
a fourth plurality of heterogeneous computational elements coupled to the third interconnection network, the fourth plurality of heterogeneous computational elements is configured for a memory operating mode for storing the first and second pluralities of configuration information. - View Dependent Claims (49, 50, 51, 52)
-
-
53. An adaptive computing integrated circuit, comprising:
-
a first plurality of heterogeneous computational elements, a first computational element of the first plurality of heterogeneous computational elements having a first fixed architecture of a plurality of fixed architectures and a second computational element of the plurality of heterogeneous computational elements having a second fixed architecture of the plurality of fixed architectures, and the plurality of fixed architectures having functions for memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability;
a first interconnection network coupled to the first plurality of heterogeneous computational elements, the first interconnection network capable of configuring the first plurality of heterogeneous computational elements for a first functional mode of a plurality of functional modes in response to first configuration information, and the first interconnection network further capable of reconfiguring the first plurality of heterogeneous computational elements for a second functional mode of the plurality of functional modes in response to second configuration information;
a second plurality of heterogeneous computational elements a third computational element of the second plurality of heterogeneous computational elements having a third fixed architecture of the plurality of fixed architectures and a fourth computational element of the second plurality of heterogeneous computational elements having a fourth fixed architecture of the plurality of fixed architectures, wherein the first, second, third and fourth fixed architectures are each different fixed architectures;
a second interconnection network coupled to the second plurality of heterogeneous computational elements, the second interconnection network capable of configuring the second plurality of heterogeneous computational elements for a third functional mode of a plurality of functional modes in response to third configuration information, and the second interconnection network further capable of reconfiguring the second plurality of heterogeneous computational elements for a fourth functional mode of the plurality of functional modes in response to fourth configuration information, wherein the first, second, third and fourth functional modes are each different functional modes of the plurality of functional modes;
a third interconnection network coupled to the first plurality of heterogeneous computational elements and to the second plurality of heterogeneous computational elements, the third interconnection network capable of selectively routing data and control information to and from the first and second pluralities of heterogeneous computational elements. - View Dependent Claims (54, 55, 56, 57, 58, 59, 60, 61, 62, 63)
-
-
64. An adaptive computing integrated circuit, comprising:
-
a first plurality of heterogeneous computational elements, a first computational element of the first plurality of heterogeneous computational elements having a first fixed architecture and a second computational element of the first plurality of heterogeneous computational elements having a second fixed architecture;
a first interconnection network coupled to the first plurality of heterogeneous computational elements, the first interconnection network capable of configuring the first plurality of heterogeneous computational elements for a first functional mode of a plurality of functional modes in response to first configuration information, and the first interconnection network further capable of reconfiguring the first plurality of heterogeneous computational elements for a second functional mode of the plurality of functional modes in response to second configuration information, and the plurality of functional modes comprising at least two of the following functional modes;
linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations;
a second plurality of heterogeneous computational elements, a third computational element of the second plurality of heterogeneous computational elements having a third fixed architecture and a fourth computational element of the second plurality of heterogeneous computational elements having a fourth fixed architecture, wherein the first, second, third and fourth fixed architectures are each different fixed architectures;
a second interconnection network coupled to the second plurality of heterogeneous computational elements, the second interconnection network capable of configuring the second plurality of heterogeneous computational elements for a third functional mode of a plurality of functional modes in response to third configuration information, and the second interconnection network further capable of reconfiguring the second plurality of heterogeneous computational elements for a fourth functional mode of the plurality of functional modes in response to fourth configuration information, wherein the first, second, third and fourth functional modes are each different functional modes of the plurality of functional modes; and
a third interconnection network coupled to the first plurality of heterogeneous computational elements and to the second plurality of heterogeneous computational elements, the third interconnection network capable of selectively routing data and control information to and from the first and second pluralities of heterogeneous computational elements. - View Dependent Claims (65, 66, 67, 68, 69, 70, 71, 72, 73, 74)
-
-
75. An adaptive computing integrated circuit, comprising:
-
a plurality of heterogeneous computational elements, a first computational element of the plurality of heterogeneous computational elements having a first fixed architecture and a second computational element of the plurality of heterogeneous computational elements having a second fixed architecture, the first fixed architecture being different than the second fixed architecture;
an interconnection network coupled to the plurality of heterogeneous computational elements, the interconnection network capable of configuring the plurality of heterogeneous computational elements for a first functional mode of a plurality of functional modes in response to first configuration information, and the interconnection network further capable of reconfiguring the plurality of heterogeneous computational elements for a second functional mode of the plurality of functional modes in response to second configuration information, the first functional mode being different than the second functional mode;
a controller coupled to the plurality of heterogeneous computational elements, the controller responsive to a plurality of configuration information to generate a plurality of control bits;
a plurality of input multiplexers, the plurality of input multiplexers responsive to the plurality of control bits to select an input line from the interconnection network for the reception of input information; and
a plurality of output demultiplexers, the plurality of output demultiplexers responsive to the plurality of control bits to select a plurality of output lines from the interconnection network for the transfer of output information. - View Dependent Claims (76)
-
-
77. An adaptive computing integrated circuit, comprising:
-
a first computational unit having a first plurality of heterogeneous computational elements forming a first reconfigurable architecture, a first computational element of the first plurality of heterogeneous computational elements having a first fixed architecture and a second computational element of the first plurality of heterogeneous computational elements having a second fixed architecture, the first fixed architecture being different than the second fixed architecture;
a first interconnection network coupled to the first plurality of heterogeneous computational elements, the first interconnection network capable of configuring the first plurality of heterogeneous computational elements for a first plurality of functional modes in response to a first plurality of configuration information;
a second computational unit having a second plurality of heterogeneous computational elements forming a second reconfigurable architecture, the second reconfigurable architecture being different than the first reconfigurable architecture, a third computational element of the second plurality of heterogeneous computational elements having a third fixed architecture and a fourth computational element of the second plurality of heterogeneous computational elements having a fourth fixed architecture, the third fixed architecture being different than the fourth fixed architecture;
a second interconnection network coupled to the second plurality of heterogeneous computational elements, the second interconnection network capable of configuring the second plurality of heterogeneous computational elements for a second plurality of functional modes in response to a second plurality of configuration information, the second plurality of functional modes being different than the first plurality of functional modes;
a third interconnection network coupled to the first computational unit and to the second computational unit, the third interconnection network capable of selectively and reconfigurably routing data and control information to the first computational unit and to the second computational unit. - View Dependent Claims (78, 79, 80, 81)
-
-
82. An adaptive computing integrated circuit, comprising:
-
a first plurality of heterogeneous computational elements forming a first reconfigurable architecture;
a first interconnection network coupled to the first plurality of heterogeneous computational elements, the first interconnection network capable of configuring and reconfiguring the first plurality of heterogeneous computational elements for a first plurality of functional modes in response to a first plurality of configuration information;
a second plurality of heterogeneous computational elements forming a second reconfigurable architecture, the second plurality of heterogeneous computational elements being different than the first plurality of heterogeneous computational elements, and the second reconfigurable architecture being different than the first reconfigurable architecture; and
a second interconnection network coupled to the second plurality of heterogeneous computational elements, the second interconnection network capable of configuring and reconfiguring the second plurality of heterogeneous computational elements for a second plurality of functional modes in response to a second plurality of configuration information, the second plurality of functional modes being different than the first plurality of functional modes. - View Dependent Claims (83, 84, 85, 86, 87, 88)
-
-
89. An adaptive computing integrated circuit, comprising:
-
a plurality of heterogeneous reconfigurable matrices, at least two heterogeneous reconfigurable matrices of the plurality of heterogeneous reconfigurable matrices comprised of distinct and different sets of a plurality of heterogeneous computational elements to form correspondingly distinct and different matrix architectures, each set of the plurality of heterogeneous computational elements coupled to a corresponding first interconnection network and configurable in response to first configuration information for a corresponding plurality of functional modes for performance of a corresponding and distinct algorithm by each of the at least two heterogeneous reconfigurable matrices; and
a matrix interconnection network coupled to the plurality of heterogeneous reconfigurable matrices, the matrix interconnection network capable of selectively and reconfigurably routing data and control to each heterogeneous reconfigurable matrix of the plurality of reconfigurable matrices, the matrix interconnection network further capable of configuring and reconfiguring the plurality of heterogeneous reconfigurable matrices, in response to second configuration information, for a plurality of operating modes. - View Dependent Claims (90, 91, 92, 93)
-
Specification